Texas Instruments TMS320C6455 specification

DDR2 Memory Controller Registerswww.ti.com

Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions (continued)

Bit	Field	Value	Description

11-9	CL		CAS latency. The value of this field defines the CAS latency, to be used when accessing
			connected SDRAM devices. A write to this field will cause the DDR2 Memory Controller to
			start the SDRAM initialization sequence. This field is writeable only when the TIMUNLOCK bit
			is unlocked. Values 0, 1, 6, and 7 are reserved for this field.
		2	CAS latency of 2.
		3	CAS latency of 3.
		4	CAS latency of 4.
		5	CAS latency of 5.

8-7	Reserved		Reserved. The reserved bit location is always read as 0. A value written to this field has no
			effect.

6-4	IBANK		Internal SDRAM bank setup bits. Defines number of banks inside connected SDRAM devices.
			A write to this bit will cause the DDR2 Memory Controller to start the SDRAM initialization
			sequence. Values 4-7 are reserved for this field.
		0	One bank SDRAM devices.
		1	Two banks SDRAM devices.
		2	Four banks SDRAM devices.
		3	Eight banks SDRAM devices.

3	Reserved		Reserved. The reserved bit location is always read as 0. A value written to this field has no
			effect.

2-0	PAGESIZE		Page size bits. Defines the internal page size of the external DDR2 memory. A write to this bit
			will cause the DDR2 Memory Controller to start the SDRAM initialization sequence. Values 4-7
			are reserved for this field.
		0	256-word page requiring 8 column address bits.
		1	512-word page requiring 9 column address bits.
		2	1024-word page requiring 10 column address bits.
		3	2048-word page requiring 11 column address bits.

42	C6455/C6454 DDR2 Memory Controller	SPRU970G – December 2005 – Revised June 2011
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Texas Instruments TMS320C6455 manual Sequence. Values 4-7 are reserved for this field

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map DDR2 Memory Controller Signal Descriptions Pin Description Command Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol Descriptions Mode Register Set MRS and Emrs DDR2 MRS and Emrs Command Refresh Mode Refresh Command Actv Command Activation Actv Dcab Command Deactivation Dcab and Deac Deac Command Read Command DDR2 Read Command Addressable Memory Ranges Write WRT CommandMemory Width, Byte Alignment, and Endianness Address Type Generated by DDR2 Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Ibank Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description DDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced Concept Command Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level Description Device and DDR2 Memory Controller Reset Relationship Self-Refresh ModeReset Considerations DDR2 Memory Controller Reset Effect Initiated by DDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration Mode Register Field Interrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event Support Using the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 Sdram Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration Field Configuring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 Configuration DDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name Description DDR2 Memory Controller Registers OffsetRegister Description Module ID and Revision Register Midr Module ID and Revision Register Midr Field DescriptionsBit Field Value Description DDR2 Memory Controller Status Register Dmcstat Ifrdy Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field Descriptions Trfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC Trrd Using this formula Todt Txsnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Txsrd Trtp Tcke Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register Dmcctl Revision History Rfid Products ApplicationsDSP TI E2E Community Home