Burst Priority Register Bprio | Texas Instruments TMS320C6455

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DDR2 Memory Controller Registers

4.7Burst Priority Register (BPRIO)

The Burst Priority Register (BPRIO) helps prevent command starvation within the DDR2 memory controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of the oldest command in the command FIFO after a set number of transfers have been made. The PRIO_RAISE bit sets the number of transfers that must be made before the DDR2 memory controller raises the priority of the oldest command. The BPRIO is shown in Figure 25 and described in Table 24. For more details on command starvation, see Section 2.7.2.

Figure 25. Burst Priority Register (BPRIO)

31				16
	Reserved
		R-0
15	8	7		0

Reserved				PRIO_RAISE
R-0				R/W-0xFF

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 24. Burst Priority Register (BPRIO) Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	000h	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

7-0	PRIO_RAISE	0h	1 memory transfer.
		1h	2 memory transfers.
		...
		FEh	255 memory transfers.
		FFh	EMIF reorders commands based on its arbitration.

SPRU970G – December 2005 – Revised June 2011	C6455/C6454 DDR2 Memory Controller	47
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Texas Instruments TMS320C6455 manual Burst Priority Register Bprio Field Descriptions, Prioraise

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Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Purpose of the Peripheral FeaturesFunctional Block Diagram Industry Standards Compliance Statement Memory Map Signal DescriptionsClock Control Pin Description DDR2 Memory Controller Signal Descriptions Protocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command Function DDR2 MRS and Emrs Command Mode Register Set MRS and Emrs Refresh Command Refresh Mode Activation Actv Actv Command Deactivation Dcab and Deac Dcab Command Deac Command DDR2 Read Command Read Command Address Type Generated by DDR2 Write WRT CommandMemory Width, Byte Alignment, and Endianness Addressable Memory Ranges Ibank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency Levels DDR2 Memory Controller Reset Effect Initiated by Self-Refresh ModeReset Considerations Device and DDR2 Memory Controller Reset Relationship Mode Register Field 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 Configuration Edma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Field Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register Sdrfc SDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2 Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet Parameter Register Description DDR2 Memory Controller RegistersOffset Bit Field Value Description Module ID and Revision Register MidrModule ID and Revision Register Midr Field Descriptions Ifrdy DDR2 Memory Controller Status Register Dmcstat Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Tras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWR Using this formula Txsrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt Txsnr Prioraise Burst Priority Register BprioBurst Priority Register Bprio Field Descriptions DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register Dmcctl Revision History TI E2E Community Home Products ApplicationsDSP Rfid