Refresh Mode, Refresh Command | Texas Instruments TMS320C6455

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Peripheral Architecture

2.4.2Refresh Mode

The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device (Figure 4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate (REFRESH_RATE) bit in the SDRAM refresh control register (SDRFC). Page information is always invalid before and after a REFR command; thus, a refresh cycle always forces a page miss. This type of refresh cycle is often called autorefresh. Autorefresh commands may not be disabled within the DDR2 memory controller. See Section 2.8 for more details on REFR command scheduling.

Figure 4. Refresh Command

REFR

DDR2CLKOUT

DDR2CLKOUT

DSDCKE

DCE0

DSDRAS

DSDCAS

DSDWE

DEA[13:0]

DBA[2:0]

DSDDQM[3:0]

SPRU970G – December 2005 – Revised June 2011	C6455/C6454 DDR2 Memory Controller	15
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Texas Instruments TMS320C6455 manual Refresh Mode, Refresh Command

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map Pin Description DDR2 Memory Controller Signal Descriptions Protocol Descriptions DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Command Function DDR2 MRS and Emrs Command Mode Register Set MRS and Emrs Refresh Command Refresh Mode Activation Actv Actv Command Deactivation Dcab and Deac Dcab Command Deac Command DDR2 Read Command Read Command Address Type Generated by DDR2 Write WRT CommandMemory Width, Byte Alignment, and Endianness Addressable Memory Ranges Ibank Bank Configuration Register Fields for Address MappingAddress Mapping Bit Field Bit Value Bit Description Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Fifo Description DDR2 Memory Controller Interface Command Ordering and Scheduling, Advanced Concept DDR2 Memory Controller Fifo Block Diagram Command Starvation Urgency Level Description Refresh SchedulingPossible Race Condition Refresh Urgency Levels DDR2 Memory Controller Reset Effect Initiated by Self-Refresh ModeReset Considerations Device and DDR2 Memory Controller Reset Relationship Mode Register Field 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration DDR2 Sdram Extended Mode Register 1 Configuration Edma Event Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Interrupt Support Connecting the DDR2 Memory Controller to DDR2 Sdram Using the DDR2 Memory Controller Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Field Programming the Sdram Configuration Register SdcfgSdcfg Configuration Programming the Sdram Refresh Control Register Sdrfc SDTIM1 Configuration DDR2 Memory Refresh SpecificationSdrfc Configuration Configuring Sdram Timing Registers SDTIM1 and SDTIM2 Name Description SDTIM2 ConfigurationDmcctl Configuration DDR2 Sdram Data Register Field Sheet Parameter DDR2 Memory Controller Registers OffsetRegister Description Module ID and Revision Register Midr Module ID and Revision Register Midr Field DescriptionsBit Field Value Description Ifrdy DDR2 Memory Controller Status Register Dmcstat Sdram Configuration Register Sdcfg Field Descriptions Sdram Configuration Register Sdcfg Sequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Refresh Control Register Sdrfc Tras TRC Trrd Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Trfc TRP Trcd TWR Using this formula Txsrd Trtp Tcke Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Todt Txsnr Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register Dmcctl Revision History TI E2E Community Home Products ApplicationsDSP Rfid