Texas Instruments TMS320C6455 manual

Introduction

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EMIFA

DDR2 memory

controller

PLL2

Other peripherals

EDMA

controller

Boot

configuration

Figure 1. Device Block Diagram

				L1P
			cache/SRAM
		L2 memory	L1 program memory controller						Advanced
		controller	Cache control						event
			Cache control						triggering
			Bandwidth management						triggering
	memory	Cache	Bandwidth management						(AET)
		control	Memory protection
		Bandwidth
resource	L2	management	C64x+ CPU
			C64x+ CPU
		Memory	IDMA		Instruction fetch
		protection	IDMA		SPLOOP buffer
central					SPLOOP buffer
				16/32−bit instruction dispatch
					Instruction decode
				Data path A				Data path B
Switched		External		Data path A				Data path B
		External
		memory	L1	S1	M1	D1	D2	M2	S2	L2
		controller	L1	S1	M1	D1	D2	M2	S2	L2
		controller
		Configuration
		Configuration		Register file A				Register file B
		registers		Register file A				Register file B
		registers
		Master
		DMA	L1 data memory controller						Interrupt
			L1 data memory controller						Interrupt
		Slave	Cache control					and exception
		DMA	Cache control						controller
			Memory protection						controller
								Power control

			Bandwidth management
			Bandwidth management
PLL2
				L1D
			cache/SRAM

1.4Industry Standard(s) Compliance Statement

The DDR2 memory controller is compliant with the JESD79-2B DDR2 SDRAM.

10	C6455/C6454 DDR2 Memory Controller	SPRU970G – December 2005 – Revised June 2011
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Copyright © 2005–2011, Texas Instruments Incorporated

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Texas Instruments TMS320C6455 manual Industry Standards Compliance Statement

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Functional Block Diagram FeaturesPurpose of the Peripheral Industry Standards Compliance Statement Clock Control Signal DescriptionsMemory Map DDR2 Memory Controller Signal Descriptions Pin Description Command Function DDR2 Sdram CommandsTruth Table for DDR2 Sdram Commands Protocol Descriptions Mode Register Set MRS and Emrs DDR2 MRS and Emrs Command Refresh Mode Refresh Command Actv Command Activation Actv Dcab Command Deactivation Dcab and Deac Deac Command Read Command DDR2 Read Command Addressable Memory Ranges Write WRT CommandMemory Width, Byte Alignment, and Endianness Address Type Generated by DDR2 Bit Field Bit Value Bit Description Bank Configuration Register Fields for Address MappingAddress Mapping Ibank Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description DDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced Concept Command Starvation Refresh Urgency Levels Refresh SchedulingPossible Race Condition Urgency Level Description Device and DDR2 Memory Controller Reset Relationship Self-Refresh ModeReset Considerations DDR2 Memory Controller Reset Effect Initiated by DDR2 Sdram Extended Mode Register 1 Configuration 11.1 DDR2 Sdram Device Mode Register Configuration ValuesDDR2 Sdram Mode Register Configuration Mode Register Field Interrupt Support 11.2 DDR2 Sdram Initialization After Reset11.3 DDR2 Sdram Initialization After Register Configuration Edma Event Support Using the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 Sdram Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Refresh Control Register Sdrfc Programming the Sdram Configuration Register SdcfgSdcfg Configuration Field Configuring Sdram Timing Registers SDTIM1 and SDTIM2 DDR2 Memory Refresh SpecificationSdrfc Configuration SDTIM1 Configuration DDR2 Sdram Data Register Field Sheet Parameter SDTIM2 ConfigurationDmcctl Configuration Name Description Offset DDR2 Memory Controller RegistersRegister Description Module ID and Revision Register Midr Field Descriptions Module ID and Revision Register MidrBit Field Value Description DDR2 Memory Controller Status Register Dmcstat Ifrdy Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field Descriptions Trfc TRP Trcd TWR Sdram Timing 1 Register SDTIM1Sdram Timing 1 Register SDTIM1 Field Descriptions Tras TRC Trrd Using this formula Todt Txsnr Sdram Timing 2 Register SDTIM2Sdram Timing 2 Register SDTIM2 Field Descriptions Txsrd Trtp Tcke Burst Priority Register Bprio Field Descriptions Burst Priority Register BprioPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register Dmcctl Revision History Rfid Products ApplicationsDSP TI E2E Community Home