Texas Instruments TMS320C6455 specs

DDR2 Memory Controller Registers

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4.8DDR2 Memory Controller Control Register (DMCCTL)

The DDR2 memory controller control register (DMCCTL) resets the interface logic of the DDR2 memory controller. The DMCCTL is shown in Figure 26 and described in Table 25.

Figure 26. DDR2 Memory Controller Control Register (DMCCTL)

31						16
	Reserved

	R-0x5000
15	6	5	4	3	2	0

Reserved

IF

RESET

Rsvd

Rsvd

RL

R/W-0x0190	R/W-	R/W- R-0x0	R/W-0x7
	0x1	0x0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 25. DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions

Bit	Field	Value	Description

31-6	Reserved		Reserved. Writes to this register must keep this field at its default value.

5	IFRESET		DDR2 memory controller interface logic reset. The interface logic controls the signals used to
			communicate with DDR2 SDRAM devices. This bit resets the interface logic. The status of this
			interface logic is shown on the DDR2 memory controller status register.
		0	Release reset.
		1	Assert reset.

4	Reserved		Reserved. Writes to this register must keep this field at its default value.

3	Reserved		Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

2-0	RL		Read latency bits. These bits must be set equal to the CAS latency + 1.

48	C6455/C6454 DDR2 Memory Controller	SPRU970G – December 2005 – Revised June 2011
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Texas Instruments TMS320C6455 manual DDR2 Memory Controller Control Register Dmcctl

Contents

Users Guide Submit Documentation Feedback Contents List of Figures List of Tables Submit Documentation Feedback Read This First Read This First Features Functional Block DiagramPurpose of the Peripheral Industry Standards Compliance Statement Signal Descriptions Clock ControlMemory Map DDR2 Memory Controller Signal Descriptions Pin Description DDR2 Sdram Commands Truth Table for DDR2 Sdram CommandsCommand Function Protocol Descriptions Mode Register Set MRS and Emrs DDR2 MRS and Emrs Command Refresh Mode Refresh Command Actv Command Activation Actv Dcab Command Deactivation Dcab and Deac Deac Command Read Command DDR2 Read Command Write WRT Command Memory Width, Byte Alignment, and EndiannessAddressable Memory Ranges Address Type Generated by DDR2 Bank Configuration Register Fields for Address Mapping Address MappingBit Field Bit Value Bit Description Ibank Logical Address-to-DDR2 Sdram Address Map for 32-Bit Sdram Logical Address-to-DDR2 Sdram Address Map DDR2 Memory Controller Interface DDR2 Memory Controller Fifo Description DDR2 Memory Controller Fifo Block Diagram Command Ordering and Scheduling, Advanced Concept Command Starvation Refresh Scheduling Possible Race ConditionRefresh Urgency Levels Urgency Level Description Self-Refresh Mode Reset ConsiderationsDevice and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated by 11.1 DDR2 Sdram Device Mode Register Configuration Values DDR2 Sdram Mode Register ConfigurationDDR2 Sdram Extended Mode Register 1 Configuration Mode Register Field 11.2 DDR2 Sdram Initialization After Reset 11.3 DDR2 Sdram Initialization After Register ConfigurationInterrupt Support Edma Event Support Using the DDR2 Memory Controller Connecting the DDR2 Memory Controller to DDR2 Sdram Connecting to Two 16-Bit DDR2 Sdram Devices Connecting to a Single 16-Bit DDR2 Sdram Device Connecting to Two 8-Bit DDR2 Sdram Devices Programming the Sdram Configuration Register Sdcfg Sdcfg ConfigurationProgramming the Sdram Refresh Control Register Sdrfc Field DDR2 Memory Refresh Specification Sdrfc ConfigurationConfiguring Sdram Timing Registers SDTIM1 and SDTIM2 SDTIM1 Configuration SDTIM2 Configuration Dmcctl ConfigurationDDR2 Sdram Data Register Field Sheet Parameter Name Description DDR2 Memory Controller Registers OffsetRegister Description Module ID and Revision Register Midr Module ID and Revision Register Midr Field DescriptionsBit Field Value Description DDR2 Memory Controller Status Register Dmcstat Ifrdy Sdram Configuration Register Sdcfg Sdram Configuration Register Sdcfg Field Descriptions Sequence. Values 4-7 are reserved for this field Sdram Refresh Control Register Sdrfc Sdram Refresh Control Register Sdrfc Field Descriptions Sdram Timing 1 Register SDTIM1 Sdram Timing 1 Register SDTIM1 Field DescriptionsTrfc TRP Trcd TWR Tras TRC Trrd Using this formula Sdram Timing 2 Register SDTIM2 Sdram Timing 2 Register SDTIM2 Field DescriptionsTodt Txsnr Txsrd Trtp Tcke Burst Priority Register Bprio Burst Priority Register Bprio Field DescriptionsPrioraise DDR2 Memory Controller Control Register Dmcctl DDR2 Memory Controller Control Register Dmcctl Revision History Products Applications DSPRfid TI E2E Community Home