Advantech PCI-1784 specifications Signal Connections, Pin Assignment, Connector Signal Description

Page 25

3.3 Signal Connections

Pin Assignment

Figure 3-2 shows the pin assignments for the 37-pin I/O connector on the PCI-1784.


EGND	1	20	CH0A-
CH0A+	2	21	CH0B-
CH0B+	3	22	CH0Z-
CH0Z+	4	23	CH1A-
CH1A+	5	24	CH1B-
CH1B+	6	25	CH1Z-
CH1Z+	7	26	CH2A-
CH2A+	8	27	CH2B-
CH2B+	9	28	CH2Z-
CH2Z+	10	29	CH3A-
CH3A+	11	30	CH3B-
CH3B+	12	31	CH3Z-
CH3Z+	13	32	EGND
IDI COM	14	33	IDI1
IDI0	15	34	IDI3
IDI2	16	35	EGND
EGND	17	36	IDO1
IDO0	18	37	IDO3
IDO2	19
			.

Fig. 3-2 I/O connector pin assignments for the PCI-1784

I/O Connector Signal Description

Table 3-2 I/O Connector Signal Description

Signal Name	Reference	Direction	Description
EGND	-	-	External Ground.
CH<0..3>A+	EGND	Input	Channel <0..3> A differential positive-input.
CH<0..3>A-	EGND	Input	Channel <0..3> A differential negative-input.
CH<0..3>B+	EGND	Input	Channel <0..3> B differential positive-input.
CH<0..3>B-	EGND	Input	Channel <0..3> B differential negative-input.
CH<0..3>Z+	EGND	Input	Channel <0..3> Z differential positive-input.
CH<0..3>Z-	EGND	Input	Channel <0..3> Z differential negative-input.
IDI<0..3>	IDI COM	Input	Isolated Digital Input, Channels 0 through 3.
IDI COM	-	-	Common input of the Isolated Digital Input.
IDO<0..3>	EGND	Output	Isolated Digital Output, Channels 0 through 3.
EGND	-	-	External Ground.

21

Image 25

Contents Page Page Contents Appendix D. Operation Introduction FeaturesEncoder Interface Digital Input and Interrupts CountersFlexible Digital Output function Special Shielded Cable for Noise ReductionBoard ID Applications Installation GuideInstallation Flow Chart Device Drivers Software OverviewRegister-level Programming Programming Tools Device Drivers Programming RoadmapProgramming with Device Drivers Function Library Troubleshooting Device Drivers ErrorWiring Cable AccessoriesWiring Boards Unpacking InstallationPage Setup Screen of Advantech Automation Software Driver InstallationSelect the Individual Drivers option Hardware InstallationPage Device name listed on the Device Manager Board selection Device Setup & Configuration‘Setup’ dialog box Setting Up and configure the deviceOperation dialog box Switch and Jumper Settings Signal ConnectionsOverview Names of Jumpers Function descriptionBoard ID setting SW1 Connector Signal Description Signal ConnectionsPin Assignment Single ended Outputs Encoder Quadrature encoder inputQuadrature encoder up/down counter input connections Isolated digital output Isolated digital inputTimer Appendix A. SpecificationsEncoder Output Counter Latch InterruptGeneral ADDRESS, Control and Data BUS Appendix B. Block DiagramPage I/O Port Address Map Appendix C. Register Structure and Format+ HEX Table C-1 PCI-1784 register format Part1CH Clock Control Table C-2 PCI-1784 Register for counter 0/1/2/3 mode Counter 0/1/2/3 mode BASE+00/04/08/0CHDI0 Table C-3 PCI-1784 Register for counter 0/1/2/3 latch data Counter 0/1/2/3 latch data BASE+00/04/08/0CHTable C-4 PCI-1784 Register for counter 0/1/2/3 compare data Counter 0/1/2/3 compare data BASE+10/14/18/1CHTable C-5 PCI-1784 Register for interrupt control Interrupt control register BASE+20HTable C-6 PCI-1784 Register for interrupt status Interrupt status register BASE+20HTable C-7 PCI-1784 Register for clock control Clear Interrupt BASE+24HTable C-8 PCI-1784 Register for clear interrupt Table C-9 PCI-1784 Register for software latch Software latch BASE+28HTable C-10 PCI-1784 Board ID data Board ID BASE+28HTable C-11 PCI-1784 Register for reset counter Reset counter BASE+2CHTable C-12 PCI-1784 Register for digital output Digital output BASE+30HTable C-13 PCI-1784 Register for digital input/output Digital input/output BASE+30HPage Quadrature encoder introduction Appendix D. OperationQuadrature input counter mode Mode Maximum input rate 8MHz 4MHz 2MHz 1MHzCounter modes Single-ended vs. differential inputPulse/direction mode Pulse modeDisabled mode Digital noise filterClock frequency Maximum width Latch modeLatch Index latchTimer function Counter reset valueInterrupt function