Advantech Clear Interrupt BASE+24H, Table C-7 PCI-1784 Register for clock control

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C.8 Clear Interrupt — BASE+24H

Table C-7 PCI-1784 Register for clock control

Base Addr.		15	14	13	12	11	10	9	8	7		6	5	4	3	2	1	0

		31	30	29	28	27	26	25	24	23		22	21	20	19	18	17	16
		31	30	29	28	27	26	25	24	23		22	21	20	19	18	17	16

									Clock Control
24H	W
24H	W																SC1	SC0

							TB2	TB1	TB0	DV7		DV6	DV5	DV4	DV3	DV2	DV1	DV0

SC1 ~ SC0	Sampling clock select
	00	8	MHz sampling clock
	01	4	MHz sampling clock
	10	2	MHz sampling clock
	11	1	MHz sampling clock
DV7 ~ DV0	Timer divider control
TB2 ~ TB0	Timer time base select
	000	50 KHz time base
	001	5	KHz time base
	010	500 Hz time base
	011	50 Hz time base
	100	5	Hz time base
	101	N/A
	110	N/A
	111	N/A

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Contents Page Page Contents Appendix D. Operation Introduction FeaturesEncoder Interface Special Shielded Cable for Noise Reduction CountersDigital Input and Interrupts Flexible Digital Output functionBoard ID Applications Installation GuideInstallation Flow Chart Device Drivers Software OverviewRegister-level Programming Programming Tools Device Drivers Programming RoadmapProgramming with Device Drivers Function Library Troubleshooting Device Drivers ErrorWiring Cable AccessoriesWiring Boards Unpacking InstallationPage Setup Screen of Advantech Automation Software Driver InstallationSelect the Individual Drivers option Hardware InstallationPage Device name listed on the Device Manager Board selection Device Setup & Configuration‘Setup’ dialog box Setting Up and configure the deviceOperation dialog box Names of Jumpers Function description Signal ConnectionsSwitch and Jumper Settings OverviewBoard ID setting SW1 Connector Signal Description Signal ConnectionsPin Assignment Single ended Outputs Encoder Quadrature encoder inputQuadrature encoder up/down counter input connections Isolated digital output Isolated digital inputTimer Appendix A. SpecificationsEncoder Output Counter Latch InterruptGeneral ADDRESS, Control and Data BUS Appendix B. Block DiagramPage I/O Port Address Map Appendix C. Register Structure and Format+ HEX Table C-1 PCI-1784 register format Part1CH Clock Control Table C-2 PCI-1784 Register for counter 0/1/2/3 mode Counter 0/1/2/3 mode BASE+00/04/08/0CHDI0 Table C-3 PCI-1784 Register for counter 0/1/2/3 latch data Counter 0/1/2/3 latch data BASE+00/04/08/0CHTable C-4 PCI-1784 Register for counter 0/1/2/3 compare data Counter 0/1/2/3 compare data BASE+10/14/18/1CHTable C-5 PCI-1784 Register for interrupt control Interrupt control register BASE+20HTable C-6 PCI-1784 Register for interrupt status Interrupt status register BASE+20HTable C-7 PCI-1784 Register for clock control Clear Interrupt BASE+24HTable C-8 PCI-1784 Register for clear interrupt Table C-9 PCI-1784 Register for software latch Software latch BASE+28HTable C-10 PCI-1784 Board ID data Board ID BASE+28HTable C-11 PCI-1784 Register for reset counter Reset counter BASE+2CHTable C-12 PCI-1784 Register for digital output Digital output BASE+30HTable C-13 PCI-1784 Register for digital input/output Digital input/output BASE+30HPage Quadrature encoder introduction Appendix D. OperationSingle-ended vs. differential input Mode Maximum input rate 8MHz 4MHz 2MHz 1MHzQuadrature input counter mode Counter modesDigital noise filter Pulse modePulse/direction mode Disabled modeIndex latch Latch modeClock frequency Maximum width LatchTimer function Counter reset valueInterrupt function