Appendix B. Block Diagram
ADDRESS, CONTROL AND DATA BUS
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| CO UNTER |
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| DIG ITAL |
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| UP/DOW N |
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| M ODE |
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| FILTER |
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| CO UNTER |
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| CO NTROL |
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| CIRCUIT | ||||
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| INPUT | ||||||||
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| ISOLATIONDIFF/SE |
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| UP/DOW N COUNTER |
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| UP/DOW N COUNTER |
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PRO GRAMM ABLECONTROL
TIM E
GENERATOR
UNIT INTERRUPT CONTROLLER
PCI INTERFACE
PCI BUS
CH .0 PHASE A
CH .0 PHASE B CH .0 INDEX
CH .1 PHASE A
CH .1 PHASE B CH .1 INDEX
CH .2 PHASE A
CH .2 PHASE B CH .2 INDEX
CH .3 PHASE A
CH .3 PHASE B CH .3 INDEX
DO /I CH .0
DO /I CH .1
DO /I CH .2 DO /I CH .3
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