Samsung M471B1G73AH0 specifications Single-ended Requirements for Differential Signals, Time

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Unbuffered SODIMM

datasheet

Rev. 1.0

DDR3 SDRAM

10.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.

CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every half-cycle.

DQS, DQS have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle proceeding and follow- ing a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD

signals, then these ac-levels apply also for the single-ended signals CK and CK .

VDD or VDDQ

VSEH min

VSEH

VDD/2 or VDDQ/2

VSEL max

VSS or VSSQ

CK or DQS

VSEL

time

Figure 3. Single-ended requirement for differential signals

Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single- ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.

[ Table 4 ] Single-ended levels for CK, DQS, CK, DQS

Symbol

Parameter

 

DDR3-800/1066/1333/1600

Unit

NOTE

 

Min

Max

 

 

 

 

 

 

 

 

VSEH

Single-ended high-level for strobes

 

(VDD/2)+0.175

NOTE3

V

1, 2

 

 

 

 

 

(VDD/2)+0.175

 

 

 

Single-ended high-level for CK, CK

 

NOTE3

V

1, 2

 

 

VSEL

Single-ended low-level for strobes

 

NOTE3

(VDD/2)-0.175

V

1, 2

 

 

 

 

 

 

(VDD/2)-0.175

 

 

Single-ended low-level for CK, CK

 

NOTE3

V

1, 2

 

 

NOTE :

1.For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS) use VIH/VIL(AC) of DQs.

2.VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here

3.These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective

limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"

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Contents Datasheet History RevFirst Release Jul Kim Table Of Contents Address Configuration Key FeaturesDDR3 Unbuffered Sodimm Ordering Information Pin Front Back X64 Dimm Pin Configurations Front side/Back SidePin Name Description Number Pin DescriptionInput/Output Functional Description Symbol Type Function8GB, 1Gx64 Module Populated as 2 ranks of x8 DDR3 SDRAMs Function Block DiagramAbsolute Maximum Ratings Dram Component Operating Temperature RangeAC & DC Operating Conditions Absolute Maximum DC RatingsAC & DC Input Measurement Levels 10.1 AC & DC Logic Input Levels for Single-ended SignalsIllustration of Vrefdc tolerance and Vref ac-noise limits Vref TolerancesDifferential Signals Definition AC and DC Logic Input Levels for Differential SignalsSymbol Parameter DDR3-800/1066/1333/1600 Unit +0.2Time Single-ended Requirements for Differential SignalsSlew rate definition for Differential Input Signals Slew Rate Definition for Single Ended Input SignalsDifferential Input Cross Point Voltage Parameter DDR3-800/1066/1333/1600 Unit Min MaxSingle Ended AC and DC Output Levels AC & DC Output Measurement LevelsDifferential AC and DC Output Levels Single-ended Output Slew RateDifferential output slew rate for rising edge Differential Output Slew RateDelta TRdiff Differential output slew rate for falling edge Delta TFdiffSymbol Description Dimm IDD specification definitionDatasheet M471B1G73AH0 8GB 1Gx64 Module IDD Spec Table14.1 2Rx8 2GB Sodimm Input/Output CapacitanceM471B1G73AH0 Parameter DDR3-1066 DDR3-1333Refresh Parameters by Device Density Electrical Characteristics and AC timingDDR3-1066 Speed Bins CL-nRCD-nRP DDR3-1333 CL-nRCD-nRP DDR3-1333 Speed BinsDDR3-1600 Speed Bins CL-nRCD-nRP Speed Bin Table Notes Absolute Specification Toper Vddq = VDD = 1.5V +/- 0.075Timing Parameters by Speed Bin Timing Parameters by Speed GradeReset Timing MIN MAX Jitter Notes ZQCorrection TSens x Tdriftrate + VSens x Vdriftrate Timing Parameter NotesX 1 + 0.15 x 15 = 0.133 ~~ 128ms 17.1 512Mx8 based 1Gx64 Module 2 Ranks M471B1G73AH0 Physical Dimensions

M471B1G73AH0 specifications

The Samsung M471B1G73AH0 is a high-performance DDR4 SO-DIMM memory module designed for laptops and compact systems. This specific RAM chip showcases a balance of speed, efficiency, and reliability, making it an ideal choice for both everyday users and professionals seeking enhanced system performance.

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In conclusion, the Samsung M471B1G73AH0 is a robust DDR4 memory solution that delivers solid performance and reliability. With its 8GB capacity, 2400 MHz frequency, and energy-efficient design, it is suitable for a wide range of computing needs, making it a popular choice among users looking to upgrade their systems for improved efficiency and responsiveness.