Samsung M471B1G73AH0 Timing Parameter Notes, ZQCorrection TSens x Tdriftrate + VSens x Vdriftrate

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Unbuffered SODIMM

datasheet

Rev. 1.0

DDR3 SDRAM

16.2 Timing Parameter Notes

1.Actual value dependant upon measurement level definitions which are TBD.

2.Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

3.The max values are system dependent.

4.WR as programmed in mode register

5.Value must be rounded-up to next higher integer value

6.There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7.For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"

8.For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".

9.tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10.WR in clock cycles as programmed in MR0

11.The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing Diagram Datasheet.

12.Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated

by TBD

13.Value is only valid for RON34

14.Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.

15.tREFI depends on TOPER

16.tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC).

See "Address/Command Setup, Hold and Derating" on component datasheet.

17.tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals, VREF(DC)= VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC).

See "Data Setup, Hold and Slew Rate Derating" on component datasheet.

18.Start of internal write transaction is defined as follows ;

For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.

For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL

For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL

19.The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram Datasheet"

20.CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations.

21.Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".

22.Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23.One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The

appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub- ject to in the application, is illustrated. The interval could be defined by the following formula:

ZQCorrection

(TSens x Tdriftrate) + (VSens x Vdriftrate)

where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu- lated as:

0.5

(1.5 x 1) + (0.15 x 15) = 0.133 ~~ 128ms

24.n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25.tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26.tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27.The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter- nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].

28.Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC)

29.tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.

30.tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.

31.tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

32.tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

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Contents Datasheet Rev HistoryFirst Release Jul Kim Table Of Contents Key Features Address ConfigurationDDR3 Unbuffered Sodimm Ordering Information X64 Dimm Pin Configurations Front side/Back Side Pin Front BackPin Description Pin Name Description NumberSymbol Type Function Input/Output Functional DescriptionFunction Block Diagram 8GB, 1Gx64 Module Populated as 2 ranks of x8 DDR3 SDRAMsAC & DC Operating Conditions Dram Component Operating Temperature RangeAbsolute Maximum Ratings Absolute Maximum DC Ratings10.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limitsSymbol Parameter DDR3-800/1066/1333/1600 Unit AC and DC Logic Input Levels for Differential SignalsDifferential Signals Definition +0.2Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals Parameter DDR3-800/1066/1333/1600 Unit Min MaxDifferential AC and DC Output Levels AC & DC Output Measurement LevelsSingle Ended AC and DC Output Levels Single-ended Output Slew RateDelta TRdiff Differential output slew rate for falling edge Differential Output Slew RateDifferential output slew rate for rising edge Delta TFdiffDimm IDD specification definition Symbol DescriptionDatasheet IDD Spec Table M471B1G73AH0 8GB 1Gx64 ModuleM471B1G73AH0 Parameter Input/Output Capacitance14.1 2Rx8 2GB Sodimm DDR3-1066 DDR3-1333Electrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins CL-nRCD-nRP DDR3-1333 Speed Bins DDR3-1333 CL-nRCD-nRPDDR3-1600 Speed Bins CL-nRCD-nRP Absolute Specification Toper Vddq = VDD = 1.5V +/- 0.075 Speed Bin Table NotesTiming Parameters by Speed Grade Timing Parameters by Speed BinReset Timing MIN MAX Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftrateX 1 + 0.15 x 15 = 0.133 ~~ 128ms Physical Dimensions 17.1 512Mx8 based 1Gx64 Module 2 Ranks M471B1G73AH0

M471B1G73AH0 specifications

The Samsung M471B1G73AH0 is a high-performance DDR4 SO-DIMM memory module designed for laptops and compact systems. This specific RAM chip showcases a balance of speed, efficiency, and reliability, making it an ideal choice for both everyday users and professionals seeking enhanced system performance.

One of the main features of the M471B1G73AH0 is its capacity. With 8GB of memory, it provides ample space for multitasking, allowing users to run multiple applications simultaneously without experiencing slowdowns. This is particularly beneficial for users who require a robust performance for tasks such as video editing, gaming, or running virtual machines.

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