Samsung M471B1G73AH0 specifications Dimm IDD specification definition, Symbol Description

Page 17

Unbuffered SODIMM

datasheet

Rev. 1.0

DDR3 SDRAM

12. DIMM IDD specification definition

Symbol

 

 

Description

 

Operating One Bank Active-Precharge Current

IDD0

CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: High between ACT and PRE;

Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:

 

0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

 

tern

 

Operating One Bank Active-Read-Precharge Current

 

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: High between ACT, RD

IDD1

and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:

 

0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

 

tern

 

 

 

Precharge Standby Current

IDD2N

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode

 

 

Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

 

Precharge Power-Down Current Slow Exit

IDD2P0

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2);

 

 

ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit3)

 

Precharge Power-Down Current Fast Exit

IDD2P1

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2);

 

 

ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit3)

 

Precharge Quiet Standby Current

IDD2Q

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2);

 

 

ODT Signal: stable at 0

 

 

 

Active Standby Current

IDD3N

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode

 

 

Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

 

Active Power-Down Current

IDD3P

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: stable at 1; Command, Address, Bank

Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2); ODT

 

 

Signal: stable at 0

 

 

 

Operating Burst Read Current

 

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: High between RD; Command, Address,

IDD4R

Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank

 

Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable

 

at 0; Pattern Details: Refer to Component Datasheet for detail pattern

 

Operating Burst Write Current

 

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: High between WR; Command, Address,

IDD4W

Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank

 

Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: stable

 

at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern

 

Burst Refresh Current

IDD5B

CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0;

CS

: High between REF; Command,

Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and

 

 

RTT: Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

 

Self Refresh Current: Normal Temperature Range

IDD6

TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Normal5); CKE: Low; External clock: Off; CK and

CK:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

 

 

Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING

 

Self-Refresh Current: Extended Temperature Range (optional)6)

IDD6ET

TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled4); Self-Refresh Temperature Range (SRT): Extended5); CKE: Low; External clock: Off; CK and

CK:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

 

 

Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2); ODT Signal: FLOATING

 

Operating Bank Interleave Read Current

IDD7

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 81); AL: CL-1;

CS

: High

between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and

 

the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:

 

Enabled in Mode Registers2); ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

 

RESET Low Current

IDD8

RESET : Low; External clock : off; CK and

CK

: LOW; CKE : FLOATING ;

CS,

Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :

 

FLOATING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

- 17 -

Page 16 Page 18
Image 17
Page 16 Page 18
Contents Datasheet First Release Jul Kim RevHistory Table Of Contents DDR3 Unbuffered Sodimm Ordering Information Key FeaturesAddress Configuration Pin Front Back X64 Dimm Pin Configurations Front side/Back SidePin Name Description Number Pin DescriptionInput/Output Functional Description Symbol Type Function8GB, 1Gx64 Module Populated as 2 ranks of x8 DDR3 SDRAMs Function Block DiagramAbsolute Maximum Ratings Dram Component Operating Temperature RangeAC & DC Operating Conditions Absolute Maximum DC RatingsAC & DC Input Measurement Levels 10.1 AC & DC Logic Input Levels for Single-ended SignalsIllustration of Vrefdc tolerance and Vref ac-noise limits Vref TolerancesDifferential Signals Definition AC and DC Logic Input Levels for Differential SignalsSymbol Parameter DDR3-800/1066/1333/1600 Unit +0.2Time Single-ended Requirements for Differential SignalsSlew rate definition for Differential Input Signals Slew Rate Definition for Single Ended Input SignalsDifferential Input Cross Point Voltage Parameter DDR3-800/1066/1333/1600 Unit Min MaxSingle Ended AC and DC Output Levels AC & DC Output Measurement LevelsDifferential AC and DC Output Levels Single-ended Output Slew RateDifferential output slew rate for rising edge Differential Output Slew RateDelta TRdiff Differential output slew rate for falling edge Delta TFdiffSymbol Description Dimm IDD specification definitionDatasheet M471B1G73AH0 8GB 1Gx64 Module IDD Spec Table14.1 2Rx8 2GB Sodimm Input/Output CapacitanceM471B1G73AH0 Parameter DDR3-1066 DDR3-1333Refresh Parameters by Device Density Electrical Characteristics and AC timingDDR3-1066 Speed Bins CL-nRCD-nRP DDR3-1333 CL-nRCD-nRP DDR3-1333 Speed BinsDDR3-1600 Speed Bins CL-nRCD-nRP Speed Bin Table Notes Absolute Specification Toper Vddq = VDD = 1.5V +/- 0.075Timing Parameters by Speed Bin Timing Parameters by Speed GradeReset Timing MIN MAX Jitter Notes X 1 + 0.15 x 15 = 0.133 ~~ 128ms Timing Parameter NotesZQCorrection TSens x Tdriftrate + VSens x Vdriftrate 17.1 512Mx8 based 1Gx64 Module 2 Ranks M471B1G73AH0 Physical Dimensions

M471B1G73AH0 specifications

The Samsung M471B1G73AH0 is a high-performance DDR4 SO-DIMM memory module designed for laptops and compact systems. This specific RAM chip showcases a balance of speed, efficiency, and reliability, making it an ideal choice for both everyday users and professionals seeking enhanced system performance.

One of the main features of the M471B1G73AH0 is its capacity. With 8GB of memory, it provides ample space for multitasking, allowing users to run multiple applications simultaneously without experiencing slowdowns. This is particularly beneficial for users who require a robust performance for tasks such as video editing, gaming, or running virtual machines.

The module operates at a frequency of 2400 MHz, tapping into the capabilities of DDR4 technology. This frequency ensures that data can be transferred quickly, enhancing overall system responsiveness. The DDR4 specification also brings improvements in power efficiency compared to its predecessor, DDR3, resulting in lower energy consumption and prolonged battery life in portable devices.

Another notable aspect of the M471B1G73AH0 is its latency. With a CAS latency of CL17, this module strikes a good balance between speed and response time, ensuring that data retrieval and execution are efficient, which is crucial for both applications and system processes.

Samsung’s advanced manufacturing technology is evident in this module, which employs 20nm process technology to produce high-density chips. This not only contributes to lower power consumption but also results in a smaller physical footprint, allowing for increased memory density in compact devices.

In terms of compatibility, the M471B1G73AH0 is designed to support a wide range of platforms. It adheres to the standard SO-DIMM form factor, making it compatible with most laptops and all-in-one systems. This versatility allows users to easily upgrade their existing systems for enhanced performance.

Additionally, the module includes features such as ECC (Error-Correcting Code) capabilities for certain variants, which helps in identifying and correcting memory errors, thereby increasing system reliability—an essential aspect for critical applications.

In conclusion, the Samsung M471B1G73AH0 is a robust DDR4 memory solution that delivers solid performance and reliability. With its 8GB capacity, 2400 MHz frequency, and energy-efficient design, it is suitable for a wide range of computing needs, making it a popular choice among users looking to upgrade their systems for improved efficiency and responsiveness.
Top Page Image Contents