Samsung M471B1G73AH0 AC & DC Output Measurement Levels, Single Ended AC and DC Output Levels

Page 15

Unbuffered SODIMM

datasheet

Rev. 1.0

DDR3 SDRAM

11. AC & DC Output Measurement Levels

11.1 Single Ended AC and DC Output Levels

[ Table 7 ] Single Ended AC and DC output levels

Symbol

Parameter

DDR3-800/1066/1333/1600

Units

NOTE

VOH(DC)

DC output high measurement level (for IV curve linearity)

0.8 x VDDQ

V

 

VOM(DC)

DC output mid measurement level (for IV curve linearity)

0.5 x VDDQ

V

 

VOL(DC)

DC output low measurement level (for IV curve linearity)

0.2 x VDDQ

V

 

VOH(AC)

AC output high measurement level (for output SR)

VTT + 0.1 x VDDQ

V

1

VOL(AC)

AC output low measurement level (for output SR)

VTT - 0.1 x VDDQ

V

1

NOTE : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2.

11.2 Differential AC and DC Output Levels

[ Table 8 ] Differential AC and DC output levels

Symbol

Parameter

DDR3-800/1066/1333/1600

Units

NOTE

VOHdiff(AC)

AC differential output high measurement level (for output SR)

+0.2 x VDDQ

V

1

VOLdiff(AC)

AC differential output low measurement level (for output SR)

-0.2 x VDDQ

V

1

NOTE : 1. The swing of +/-0.2xVDDQis based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.

11.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in below.

[ Table 9 ] Single ended Output slew rate definition

Description

Measured

 

Defined by

From

To

 

 

 

 

 

Single ended output slew rate for rising edge

VOL(AC)

VOH(AC)

 

VOH(AC)-VOL(AC)

 

 

Delta TRse

 

 

 

 

 

 

 

 

 

 

Single ended output slew rate for falling edge

VOH(AC)

VOL(AC)

 

VOH(AC)-VOL(AC)

 

 

Delta TFse

 

 

 

 

 

 

 

 

 

 

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 10 ] Single ended output slew rate

Parameter

Symbol

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

Units

Min

Max

Min

Max

Min

Max

Min

Max

 

 

 

Single ended output slew rate

SRQse

2.5

5

2.5

5

2.5

5

2.5

5

V/ns

 

 

 

 

 

 

 

 

 

 

 

Description : SR : Slew Rate

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

se : Single-ended Signals For Ron = RZQ/7 setting

VOHdiff(AC)

VTT

VOLdiff(AC)

delta TFdiff

delta TRdiff

Figure 6. Single-ended output slew rate definition

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Image 15
Contents Datasheet Rev HistoryFirst Release Jul Kim Table Of Contents Key Features Address ConfigurationDDR3 Unbuffered Sodimm Ordering Information Pin Front Back X64 Dimm Pin Configurations Front side/Back SidePin Name Description Number Pin DescriptionInput/Output Functional Description Symbol Type Function8GB, 1Gx64 Module Populated as 2 ranks of x8 DDR3 SDRAMs Function Block DiagramAbsolute Maximum DC Ratings Dram Component Operating Temperature RangeAbsolute Maximum Ratings AC & DC Operating ConditionsAC & DC Input Measurement Levels 10.1 AC & DC Logic Input Levels for Single-ended SignalsIllustration of Vrefdc tolerance and Vref ac-noise limits Vref Tolerances +0.2 AC and DC Logic Input Levels for Differential Signals Differential Signals Definition Symbol Parameter DDR3-800/1066/1333/1600 UnitTime Single-ended Requirements for Differential SignalsParameter DDR3-800/1066/1333/1600 Unit Min Max Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals Differential Input Cross Point VoltageSingle-ended Output Slew Rate AC & DC Output Measurement LevelsSingle Ended AC and DC Output Levels Differential AC and DC Output LevelsDelta TFdiff Differential Output Slew RateDifferential output slew rate for rising edge Delta TRdiff Differential output slew rate for falling edgeSymbol Description Dimm IDD specification definitionDatasheet M471B1G73AH0 8GB 1Gx64 Module IDD Spec TableDDR3-1066 DDR3-1333 Input/Output Capacitance14.1 2Rx8 2GB Sodimm M471B1G73AH0 ParameterRefresh Parameters by Device Density Electrical Characteristics and AC timingDDR3-1066 Speed Bins CL-nRCD-nRP DDR3-1333 CL-nRCD-nRP DDR3-1333 Speed BinsDDR3-1600 Speed Bins CL-nRCD-nRP Speed Bin Table Notes Absolute Specification Toper Vddq = VDD = 1.5V +/- 0.075Timing Parameters by Speed Bin Timing Parameters by Speed GradeReset Timing MIN MAX Jitter Notes Timing Parameter Notes ZQCorrection TSens x Tdriftrate + VSens x VdriftrateX 1 + 0.15 x 15 = 0.133 ~~ 128ms 17.1 512Mx8 based 1Gx64 Module 2 Ranks M471B1G73AH0 Physical Dimensions