Samsung M471B1G73AH0 specifications AC and DC Logic Input Levels for Differential Signals, +0.2

Unbuffered SODIMM

datasheet

Rev. 1.0

DDR3 SDRAM

10.3 AC and DC Logic Input Levels for Differential Signals

10.3.1 Differential Signals Definition

				tDVAC
	CK-CK)	VIH.DIFF.AC.MIN
		VIH.DIFF.MIN
	DQS-DQS,
		0.0
(i.e.
			half cycle
Voltage		VIL.DIFF.MAX
Input
Differential		VIL.DIFF.AC.MAX
					tDVAC
						time

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

10.3.2 Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS)

Symbol	Parameter	DDR3-800/1066/1333/1600		unit	NOTE
		min	max
VIHdiff	differential input high	+0.2	NOTE 3	V	1
VILdiff	differential input low	NOTE 3	-0.2	V	1
VIHdiff(AC)	differential input high ac	2 x (VIH(AC) - VREF)	NOTE 3	V	2
VILdiff(AC)	differential input low ac	NOTE 3	2 x (VIL(AC) - VREF)	V	2

NOTE :

1.Used to define a differential signal slew-rate.

2.for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3.These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended sig- nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"

[ Table 3 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS.

Slew Rate [V/ns]	tDVAC [ps] @ VIH/Ldiff(AC) = 350mV		tDVAC [ps] @ VIH/Ldiff(AC) = 300mV
	min	max	min	max
> 4.0	75	-	175	-
4.0	57	-	170	-
3.0	50	-	167	-
2.0	38	-	163	-
1.8	34	-	162	-
1.6	29	-	161	-
1.4	22	-	159	-
1.2	13	-	155	-
1.0	0	-	150	-
< 1.0	0	-	150	-

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