Samsung M471B1G73AH0 specifications Slew Rate Definition for Single Ended Input Signals

Page 14

Unbuffered SODIMM

datasheet

Rev. 1.0

DDR3 SDRAM

10.3.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS.

VDD

CK, DQS

VIX

VDD/2

VIX

VIX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CK, DQS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4. VIX Definition

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[ Table 5 ] Cross point voltage for differential input signals (CK, DQS)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

 

 

 

Parameter

 

 

DDR3-800/1066/1333/1600

Unit

NOTE

 

 

 

 

 

 

Min

 

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-150

 

150

mV

 

Differential Input Cross Point Voltage relative to VDD/2 for CK,CK

 

 

 

 

 

-175

 

175

mV

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIX

Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS

 

 

-150

 

150

mV

 

NOTE :

1.Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing VSEL / VSEH of at least VDD/2 ±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.

10.4 Slew Rate Definition for Single Ended Input Signals

See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals. See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.

10.5 Slew rate definition for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.

[ Table 6 ] Differential input slew rate definition

Description

Measured

 

Defined by

From

 

To

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VILdiffmax

 

VIHdiffmin

 

VIHdiffmin - VILdiffmax

 

Differential input slew rate for rising edge (CK-CK and DQS-DQS)

 

 

 

Delta TRdiff

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIHdiffmin

 

VILdiffmax

 

VIHdiffmin - VILdiffmax

 

Differential input slew rate for falling edge (CK-CK and DQS-DQS)

 

 

 

Delta TFdiff

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE : The differential signal (i.e. CK -

 

and DQS -

 

 

 

must be linear between these thresholds

 

 

 

 

CK

DQS)

 

 

 

 

 

VIHdiffmin

 

0

 

VILdiffmax

delta TFdiff

delta TRdiff

Figure 5. Differential input slew rate definition for DQS, DQS and CK, CK

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Contents Datasheet First Release Jul Kim RevHistory Table Of Contents DDR3 Unbuffered Sodimm Ordering Information Key FeaturesAddress Configuration X64 Dimm Pin Configurations Front side/Back Side Pin Front BackPin Description Pin Name Description NumberSymbol Type Function Input/Output Functional DescriptionFunction Block Diagram 8GB, 1Gx64 Module Populated as 2 ranks of x8 DDR3 SDRAMsAC & DC Operating Conditions Dram Component Operating Temperature RangeAbsolute Maximum Ratings Absolute Maximum DC Ratings10.1 AC & DC Logic Input Levels for Single-ended Signals AC & DC Input Measurement LevelsVref Tolerances Illustration of Vrefdc tolerance and Vref ac-noise limitsSymbol Parameter DDR3-800/1066/1333/1600 Unit AC and DC Logic Input Levels for Differential SignalsDifferential Signals Definition +0.2Single-ended Requirements for Differential Signals TimeDifferential Input Cross Point Voltage Slew Rate Definition for Single Ended Input SignalsSlew rate definition for Differential Input Signals Parameter DDR3-800/1066/1333/1600 Unit Min MaxDifferential AC and DC Output Levels AC & DC Output Measurement LevelsSingle Ended AC and DC Output Levels Single-ended Output Slew RateDelta TRdiff Differential output slew rate for falling edge Differential Output Slew RateDifferential output slew rate for rising edge Delta TFdiffDimm IDD specification definition Symbol DescriptionDatasheet IDD Spec Table M471B1G73AH0 8GB 1Gx64 ModuleM471B1G73AH0 Parameter Input/Output Capacitance14.1 2Rx8 2GB Sodimm DDR3-1066 DDR3-1333Electrical Characteristics and AC timing Refresh Parameters by Device DensityDDR3-1066 Speed Bins CL-nRCD-nRP DDR3-1333 Speed Bins DDR3-1333 CL-nRCD-nRPDDR3-1600 Speed Bins CL-nRCD-nRP Absolute Specification Toper Vddq = VDD = 1.5V +/- 0.075 Speed Bin Table NotesTiming Parameters by Speed Grade Timing Parameters by Speed BinReset Timing MIN MAX Jitter Notes X 1 + 0.15 x 15 = 0.133 ~~ 128ms Timing Parameter NotesZQCorrection TSens x Tdriftrate + VSens x Vdriftrate Physical Dimensions 17.1 512Mx8 based 1Gx64 Module 2 Ranks M471B1G73AH0

M471B1G73AH0 specifications

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