HP XA manual AGP Bus Interface, Read/Write Buffers, System Clocking, Main Memory Controller

2 System Board

Chip-Set

AGP Bus Interface	A controller for the AGP (Accelerated Graphics Port) slot is integrated in the
	440LX PAC chip. The PAC chip supports only a synchronous AGP interface,
	coupling to the host bus frequency. The AGP characteristics are described in
	detail in “Accelerated Graphics Port (AGP) Controller” on page 41.
Main Memory Controller	The main memory controller supports three DIMM slots. Each slot can host
	a 168-pin unbuffered SDRAM module, running at 66MHz, for a total of up to
	348 MB of dynamic random access memory (ECC SDRAM).
	The memory bus is 72-bits wide, comprised of 64 bits of data and 8 bits of
	ECC. Refer to “Main Memory Bus” on page 38, for more detail on the main
	memory.
Read/Write Buffers	The PAC chip defines a data buffering scheme to support the required level
	of concurrent operations and provide adequate sustained bandwidth
	between the DRAM subsystem and all other system interfaces (CPU, AGP
	and PCI).
System Clocking	The PAC chip operates the host interface at 66MHz, PCI at 33 MHz and AGP
	at 66/133 MHz. Coupling between all interfaces and internal logic is done in a
	synchronous manner. The PAC chip is not designed to support host bus
	frequencies lower than 66 MHz. The clocking scheme uses an external clock
	synthesizer (which produces reference clocks for the host, AGP and PCI
	interfaces).

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