5
Order in Which the Tests are Performed
Checkpoint | POST Routine Description | |
Code | ||
| ||
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| |
2Ah | Clear 512 KB base RAM | |
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| |
32h | Test CPU | |
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| |
33h | Initialize POST Dispatch Manager | |
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34h | Test CMOS RAM | |
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| |
35h | Initialize alternate chipset registers | |
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| |
36h | Warm start shutdown | |
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| |
37h | Reinitialize the chipset (MB only) | |
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| |
38h | Shadow system BIOS ROM | |
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| |
39h | Reinitialize the cache (MB only) | |
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| |
3Ah | Autosize cache | |
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| |
3Ch | Configure advanced chipset registers | |
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| |
3Dh | Load alternate registers with CMOS values | |
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| |
40h | Set initial CPU speed | |
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42h | Initialize interrupt vectors | |
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44h | Initialize BIOS interrupts | |
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45h | POST device initialization | |
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| |
47h | Initialize manager for PCI Option ROMs (Rel. 5.1 and earlier) | |
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48h | Check video configuration against CMOS | |
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49h | Initialize PCI bus and devices | |
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4Ah | Initialize all video adapters in system | |
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4Bh | Display QuietBoot screen | |
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4Ch | Shadow video BIOS ROM | |
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| |
4Eh | Display BIOS copyright notice | |
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| |
50h | Display CPU type | |
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| |
51h | Initialize EISA board | |
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88