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Intel 253668-032US Manual
806 pages 5.71 Mb
2 ii3 CHAPTER 1 ABOUT THIS MANUALCHAPTER 2 SYSTEM ARCHITECTURE OVERVIEW 4 CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENTCHAPTER 4 PAGING 5 CHAPTER 5 PROTECTION6 CHAPTER 6 INTERRUPT AND EXCEPTION HANDLING7 CHAPTER 7 TASK MANAGEMENT8 CHAPTER 8 MULTIPLE-PROCESSOR MANAGEMENT9 CHAPTER 9 PROCESSOR MANAGEMENT AND INITIALIZATION11 CHAPTER 10 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)12 CHAPTER 11 MEMORY CACHE CONTROL13 CHAPTER 12 INTEL MMX TECHNOLOGY SYSTEM PROGRAMMINGCHAPTER 13 SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES 14 CHAPTER 14 POWER AND THERMAL MANAGEMENTCHAPTER 15 MACHINE-CHECK ARCHITECTURE 16 CHAPTER 16 DEBUGGING, PROFILING BRANCHES AND TIME-STAMP COUNTER17 CHAPTER 17 8086 EMULATION18 CHAPTER 18 MIXING 16-BIT AND 32-BIT CODECHAPTER 19 ARCHITECTURE COMPATIBILITY 20 CHAPTER 20 INTRODUCTION TO VIRTUAL-MACHINE EXTENSIONS21 CHAPTER 21 VIRTUAL-MACHINE CONTROL STRUCTURES22 CHAPTER 22 VMX NON-ROOT OPERATIONCHAPTER 23 VM ENTRIES 23 CHAPTER 24 VM EXITS24 CHAPTER 25 VMX SUPPORT FOR ADDRESS TRANSLATIONCHAPTER 26 SYSTEM MANAGEMENT MODE 25 CHAPTER 27 VIRTUAL-MACHINE MONITOR PROGRAMMING CONSIDERATIONS26 CHAPTER 28 VIRTUALIZATION OF SYSTEM RESOURCES27 CHAPTER 29 HANDLING BOUNDARY CONDITIONS IN A VIRTUAL MACHINE MONITORCHAPTER 30 PERFORMANCE MONITORING 29 APPENDIX A PERFORMANCE-MONITORING EVENTSAPPENDIX B MODEL-SPECIFIC REGISTERS (MSRS) 30 APPENDIX C MP INITIALIZATION FOR P6 FAMILY PROCESSORSAPPENDIX D PROGRAMMING THE LINT0 AND LINT1 INPUTS APPENDIX E INTERPRETING MACHINE-CHECK ERROR CODES 31 APPENDIX F APIC BUS MESSAGE FORMATSAPPENDIX G VMX CAPABILITY REPORTING FACILITY APPENDIX H FIELD ENCODING IN VMCS 33 FIGURES38 TABLES45 CHAPTER 1 ABOUT THIS MANUAL57 CHAPTER 2 SYSTEM ARCHITECTURE OVERVIEW91 CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT113 CHAPTER 4 PAGING4.1 PAGING MODES AND CONTROL BITS 114 115 4.1.2 Paging-Mode EnablingTable 4-1. Properties of Different Paging Modes 116 Figure 4-1. Enabling and Changing Paging Modes 117 4.1.3 Paging-Mode Modifiers 119 4.2 HIERARCHICAL PAGING STRUCTURES: AN OVERVIEW120 4.3 32-BIT PAGING 122 Figure 4-2. Linear-Address Translation to a 4-KByte Page using 32-Bit Paging Table 4-3. Use of CR3 with 32-Bit Paging (Contd.) 123 125 127 4.4 PAE PAGINGFigure 4-4. Formats of CR3 and Paging-Structure Entries with 32-Bit Paging 4.4.1 PDPTE Registers 128 Table 4-7. Use of CR3 with PAE Paging 4.4.2 Linear-Address Translation with PAE Paging 129 Table 4-8. Format of an PAE Page-Directory-Pointer-Table Entry (PDPTE) 130 the physical address specified in bits 51:12 of PDPTEi (see Table4-8 in Section Figure 4-5. Linear-Address Translation to a 4-KByte Page using PAE Paging Figure 4-6. Linear-Address Translation to a 2-MByte Page using PAE Paging 131 135 4.5 IA-32E PAGINGAddress of page-directory-pointer table Figure 4-7. Formats of CR3 and Paging-Structure Entries with PAE Paging 136 Table 4-12. Use of CR3 with IA-32e Paging 137 Figure 4-8. Linear-Address Translation to a 4-KByte Page using IA-32e Paging 140 Table 4-15. Format of an IA-32e Page-Directory Entry that Maps a 2-MByte Page 141 Table 4-15. Format of an IA-32e Page-Directory Entry that Maps a 2-MByte Page 142 Table 4-16. Format of an IA-32e Page-Directory Entry that References a Page Table 143 Table 4-17. Format of an IA-32e Page-Table Entry that Maps a 4-KByte Page 144 4.6 ACCESS RIGHTS 146 4.7 PAGE-FAULT EXCEPTIONS147 Figure 4-11. Page-Fault Error Code 148 4.8 ACCESSED AND DIRTY FLAGS149 4.9 PAGING AND MEMORY TYPING 150 4.9.3 Caching Paging-Related Information about Memory Typing 4.10 CACHING TRANSLATION INFORMATION4.10.1 Translation Lookaside Buffers (TLBs)4.10.1.1 Page Numbers, Page Frames, and Page Offsets 151 4.10.1.2 Caching Translations in TLBs 152 155 4.10.2.2 Using the Paging-Structure Caches to Translate Linear Addresses 156 4.10.2.3 Multiple Cached Entries for a Single Paging-Structure Entry 157 4.10.3 Invalidation of TLBs and Paging-Structure Caches4.10.3.1 Operations that Invalidate TLBs and Paging-Structure Caches 158 160 4.10.3.3 Optional Invalidation 161 4.10.4 Propagation of Paging-Structure Changes to Multiple 162 163 4.11 INTERACTIONS WITH VIRTUAL-MACHINE EXTENSIONS (VMX)4.11.2 VMX Support for Address Translation 164 4.12 USING PAGING FOR VIRTUAL MEMORY4.13 MAPPING SEGMENTS TO PAGES 167 CHAPTER 5 PROTECTION215 CHAPTER 6 INTERRUPT AND EXCEPTION HANDLING228 +6.11 IDT DESCRIPTORSFigure 6-1. Relationship of the IDTR and IDT INTERRUPT AND EXCEPTION HANDLING 229 6.12 EXCEPTION AND INTERRUPT HANDLING231 233 6.12.1.2 Flag Usage By Exception- or Interrupt-Handler Procedure 6.12.2 Interrupt Tasks 234 235 6.13 ERROR CODEFigure 6-5. Interrupt Task Switch 236 6.14 EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE237 250 260 Interrupt 12Stack Fault Exception (#SS) 262 Interrupt 14Page-Fault Exception (#PF) 268 269 Figure 6-9. Page-Fault Error Code 270 272 Interrupt 17Alignment Check Exception (#AC) 274 Table 6-7. Alignment Requirements by Data Type 275 278 281 283 CHAPTER 7 TASK MANAG EMENT307 CHAPTER 8 MULTIPLE-PROCESSOR MANAGEMENT381 CHAPTER 9 PROCESSOR MANAGEMENT AND INITIALIZATION447 CHAPTER 10 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)515 CHAPTER 11 MEMORY CACHE CONTROL567 CHAPTER 12 INTEL MMX TECHNOLOGY SYSTEM PROGRAMMING12.1 EMULATION OF THE MMX INSTRUCTION SET 12.2 THE MMX STATE AND MMX REGISTER ALIASINGTable 1 2-1. Acti on Take n By MMX Instructions for Different Combinations of EM, MP and TS 568 Figure 12-1. Mapping of MMX Registers to Floating-Point Registers 569 12.2.1 Effect of MMX, x87 FPU, FXSAVE, and FXRSTOR Instructions on the x87 FPU Tag WordTable 12-2. Effects of MMX Instructions on x87 FPU State 570 12.3 SAVING AND RESTORING THE MMX STATE AND REGISTERSTable 12-3. Effect of the MMX, x87 FPU, and FXSAVE/FXRSTOR Instructions on the x87 FPU Tag Word 571 12.4 SAVING MMX STATE ON TASK OR CONTEXT SWITCHES 12.5 EXCEPTIONS THAT CAN OCCUR WHEN EXECUTING MMX INSTRUCTIONS 572 12.5.1 Effect of MMX Instructions on Pending x87 Floating-Point Exceptions 12.6 DEBUGGING MMX CODE 575 CHAPTER 13 SYSTEM PROGRAMMING FOR INSTRUCTION SET EXTENSIONS AND PROCESSOR EXTENDED STATES 13.1 PROVIDING OPERATING SYSTEM SUPPORT FOR SSE/SSE2/SSE3/SSSE3/SSE4 EXTENSIONS13.1.1 Adding Support to an Operating System for SSE/SSE2/SSE3/SSSE3/SSE4 Extensions 13.1.2 Checking for SSE/SSE2/SSE3/SSSE3/SSE4 Extension Support 576 13.1.3 Checking for Support for the FXSAVE and FXRSTOR Instructions 577 13.1.4 Initialization of the SSE/SSE2/SSE3/SSSE3/SSE4 Extensions 578 Table 13-1. Action Taken for Combinations of OSFXSR, OSXMMEXCPT, SSE, SSE2, SSE3, EM, MP, and TS 579 Table 13-2. Action Taken for Combinations of OSFXSR, SSSE3, SSE4, EM, and TS 580 584 586 13.6 XSAVE/XRSTOR AND PROCESSOR EXTENDED STATE MANAGEMENT 587 589 13.7 INTEROPERA BILITY OF XSAVE/XR STOR AND FXSAVE/FXRSTOR591 13.8 DETECTION, ENUMERATION, ENABLING PROCESSOR EXTENDED STATE SUPPORTFigure 13-3. OS Enabling of Processor Extended State Support 13.8.1 Application Programming Model and Processor Extended States 592 595 CHAPTER 14 POWER AND THERMAL MANAGEMENT617 CHAPTER 15 MACHINE-CHECK ARCHITECTURE15.1 MACHINE-CHECK ARCHITECTURE 618 15.2 COMPATIBILITY WITH PENTIUM PROCESSOR 15.3 MACHINE-CHECK MSRS 620 Figure 15-2. IA32_MCG_CAP Register The effect of writing to the IA32_MCG_CAP MSR is undefined. 15.3.1.2 IA32_MCG_STATUS MSRFigure 15-3. IA32_MCG_STATUS Register Bits 63:03 in IA32_MCG_STATUS are reserved. 621 624 Figure 15-5. IA32_MCi_STATUS Register 626 629 15.3.2.5 IA32_MCi_CTL2 MSRs 630 633 634 15.4 ENHANCED CACHE ERROR REPORTING15.5 CORRECTED MACHINE CHECK ERROR INTERRUPT 637 15.5.2 System Software Recommendation for Managing CMCI and Machine Check Resources15.5.2.1 CMCI Initialization 638 15.5.2.2 CMCI Threshold Management IA32_MCi_CTL2[15:0]. This will cause overflow 15.5.2.3 CMCI Interrupt Handler 639 15.6 RECOVERY OF UNCORRECTED RECOVERA BLE (UCR) ERRORS 15.6.1 Detection of Software Error Recovery Support 15.6.2 UCR Error Reporting and Logging 640 641 15.6.3 UCR Error ClassificationWith the S and AR flag encoding in the IA32_MCi_STATUS register, UCR errors can be classified as: 642 15.6.4 UCR Error Overwrite Rules 643 644 15.7 MACHINE-CHECK AVAILABILITY15.8 MACHINE-CHECK INITIALIZATION 645 15.9 INTERPRETING THE MCA ERROR CODES647 650 654 15.9.4 Multiple MCA Errors 655 15.9.5 Machine-Check Error Codes Interpretation 15.10 GUIDELINES FOR WRITING MACHINE-CHECK SOFTWARE 657 Example 15-2 gives typical steps carried out by a machine-check exception handler. 15.10.2 Pentium Processor Machine-Check Exception Handling 15.10.3 Logging Correctable Machine-Check Errors 658 661 663 Example 15-4 gives pseudocode for an MC exception handler that supports recovery of UCR. 15.10.4.2 Corrected Machine-Check Handler for Error Recovery 666 669 CHAPTER 16 DEBUGGING, PROFILING BRANCHES AND TIME- STAMP COUNTERVol. 3 16-3 671 DR0 DR1 DR3 generated. Figure 16-1. Debug RegistersThe following paragraphs describe the functions of flags and fields in the debug registers. 16.2.1 Debug Address Registers (DR0-DR3) 16.2.2 Debug Registers DR4 and DR5 16.2.3 Debug Status Register (DR6) 672 674 677 16.3 DEBUG EXCEPTIONSFigure 16-2. DR6/DR7 Layout on Processors Supporting Intel 64 Technology 16.3.1 Debug Exception (#DB)Interrupt Vector 1 679 682 16.4 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING OVERVIEW683 Figure 16-3. IA32_DEBUGCTL MSR for Processors based on Intel Core microarchitecture 684 16.4.2 Monitoring Branches, Exceptions, and Interrupts 16.4.3 Single-Stepping on Branches, Exceptions, and Interrupts 685 16.4.4 Branch Trace Messages16.4.5 Branch Trace Store (BTS) 16.4.6 CPL-Qualified Branch Trace Mechanism 16.4.7 Freezing LBR and Performance Counters on PMI 686 687 691 Figure 16-5. DS Save Area 692 Figure 16-6. 32-bit Branch Trace Record Format 696 16.4.9.2 Setting Up the DS Save Area 697 16.4.9.3 Setting Up the BTS BufferTable 16-4. IA32_DEBUGCTL Flag Encodings 698 16.4.9.4 Setting Up CPL-Qualified BTS Table 16-5. CPL-Qualified Branch Trace Store Encodings 16.4.9.5 Writing the DS Interrupt Service Routine 699 Table 16-5. CPL-Qualified Branch Trace Store Encodings (Contd.) 702 16.6.1 LBR StackFigure 16-11. IA32_DEBUGCTL MSR for Processors based on Intel microarchitecture (Nehalem) Table 16-8. LBR Stack Size and TOS Pointer Range 703 16.6.2 Filtering of Last Branch RecordsTable 16-6. IA32_LASTBRACH_x_FROM_IP Table 16-7. IA32_LASTBRACH_x_TO_IP Table 16-9. MSR_LBR_SELECT 705 706 Figure 16-12. MSR_DEBUGCTLA MSR for Pentium4 and Intel Xeon Processors 16.7.2 LBR Stack for Processors Based on Intel NetBurst Microarchitecture 707 710 Figure 16-14. IA32_DEBUGCTL MSR for Intel Core Solo and Intel Core Duo Processors 711 16.9 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (PENTIUM M PROCESSORS)Figure 16-15. LBR Branch Record Layout for the Intel Core Solo and Intel Core Duo Processor 712 Figure 16-16. MSR_DEBUGCTLB MSR for Pentium M Processors 713 16.10 LAST BRANCH, INTERRUPT, AND EXCEPTION RECORDING (P6 FAMILY PROCESSORS)Figure 16-17. LBR Branch Record Layout for the Pentium M Processor 16.10.1 DEBUGCTLMSR Register 714 Figure 16-18. DEBUGCTLMSR Register (P6 Family Processors) 716 16.11 TIME-STAMP COUNTER 719 CHAPTER 17 8086 EMULATION 17.1 REAL-ADDRESS MODE 721 724 17.1.4 Interrupt and Exception Handling 726 17.2 VIRTUAL-8086 MODETable 17-1. Real-Address Mode Exceptions and Interrupts 17.2.1 Enabling Virtual-8086 Mode 727 17.2.2 Structure of a Virtual-8086 Task Table 17-1. Real-Address Mode Exceptions and Interrupts (Contd.) 728 17.2.3 Paging of Virtual-8086 Tasks 729 17.2.4 Protection within a Virtual-8086 Task 17.2.5 Entering Virtual-8086 Mode 732 17.2.7 Sensitive Instructions 17.2.8 Virtual-8086 Mode I/O 733 17.2.8.1 I/O-Port-Mapped I/O 17.2.8.2 Memory-Mapped I/O 734 17.2.8.3 Special I/O Buffers 17.3 INTERRUPT AND EXCEPTION HANDLING IN VIRTUAL-8086 MODE 736 17.3.1 Class 1Hardware Interrupt and Exception Handling in Virtual-8086 Mode17.3.1.1 Handling an Interrupt or Exception Through a Protected-Mode Trap or Interrupt Gate 738 740 742 17.3.3 Class 3Software Interrupt Handling in Virtual-8086 Mode 743 748 17.4 PROTECTED-MODE VIRTUAL INTERRUPTS751 CHAPTER 18 MIXING 16-BIT AND 32-BIT CODE Table 18-1. Characteristics of 16-Bit and 32-Bit Program Modules 753 757 758 18.4.2.2 Passing Parameters With a Gate 18.4.3 Interrupt Control Transfers 18.4.4 Parameter Translation 18.4.5 Writing Interface Procedures 759 761 CHAPTER 19 ARCHITECTURE COMPATIBILITY
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