Vol. 3 4-45
PAGING
(Any of the above steps would be skipped if the processor does not support the cache
in question.)
If the processor does not find a TLB or paging-structure-cache entry for the linear
address, it uses the linear address to traverse the entire paging-structure hierarchy,
as described in Section 4.3, Section 4.4.2, and Section 4.5.

4.10.2.3 Multiple Cached Entries for a Single Paging-Structure Entry

Note that multiple cached entries (in the paging-structure caches or TLBs) may
contain information derived from a single paging-structure entry. The following items
give some examples for IA-32e paging:
•Suppose that two PML4Es contain the same physical address and thus reference
the same page-directory-pointer table. Any PDPTE in that table may result in two
PDPTE-cache entries, each associated with a different set of linear addresses.
Specifically, suppose that the n1th and n2th entries in the PML4 table contain the
same physical address. This implies that the physical address in the mth PDPTE in
the page-directory-pointer table would appear in the PDPTE-cache entries
associated with both p1 and p2, where (p1» 9) = n1, (p2» 9) = n2, and (p1&
1FFH) = (p2& 1FFH) = m. This is because both PDPTE-cache entries use the
same PDPTE, one resulting from a reference from the n1th PML4E and one from
the n2th PML4E.
•Suppose that the first PML4E (i.e., the one in position 0) contains the physical
address X in CR3 (the physical address of the PML4 table). This implies the
following:
— Any PML4-cache entry associated with linear addresses with 0 in bits 47:39
contains address X.
— Any PDPTE-cache entry associated with linear addresses with 0 in bits 47:30
contains address X. This is because the translation for a linear address for
which the value of bits 47:30 is 0 uses the value of bits 47:39 (0) to locate a
page-directory-pointer table at address X (the address of the PML4 table). It
then uses the value of bits 38:30 (also 0) to find address X again and to store
that address in the PDPTE-cache entry.
— Any PDE-cache entry associated with linear addresses with 0 in bits 47:21
contains address X for similar reasons.
— Any TLB entry for page number 0 (associated with linear addresses with 0 in
bits 47:12) translates to page frame X » 12 for similar reasons.
The same PML4E contributes its address X to all these cache entries because the
self-referencing nature of the entry causes it to be used as a PML4E, a PDPTE, a
PDE, and a PTE.