Cypress CY7C1361C, CY7C1363C manual

Contents

Main 9-Mbit ( 256K x 36/512K x 18 ) Flow-Throu Logic Block Diagram CY7C1361C (256K x 36) ADDRESS REGISTER ADV CLK BURST COUNTER AND LOGIC CLR ZZ A BWE CY7C1361C CY7C1363C Document #: 38-05541 Rev. *F Page 3 of 31 Pin Configurations CY7C1361C (256K x 36) CY7C1363C (512K x 18) 100-Pin TQFP Pinout (2 Chip Enables) (AJ Version) CY7C1363C (512K x 18) CY7C1361C (256K x 36) 119-Ball BGA Pinout (2 Chip Enables with JTAG) CY7C1361C CY7C1363C 165-Ball FBGA Pinout (3 Chip Enable) CY7C1363C (512K x 18) CY7C1361C (256K x 36) 2345671 A B C D E F G H J K L M N P R CY7C1361C CY7C1363C Pin Definitions Functional Overview Burst Sequences Interleaved Burst Address Table (MODE = Floating or VDD) Linear Burst Address Table (MODE = GND) ZZ Mode Electrical Characteristics Truth Table Partial Truth Table for Read/Write Truth Table for Read/Write IEEE 1149.1 Serial Boundary Scan (JTAG) TAP Controller State Diagram TAP Controller Block Diagram CY7C1361C CY7C1363C TAP Ti ming TAP AC Switching Characteristics 3.3V TAP AC Test Conditions 3.3V TAP AC Output Load Equivalent F DO T Scan Register Sizes Identification Codes 119-Ball BGA Boundary Scan Order 165-Ball FBGA Boundary Scan Order Maximum Ratings Operating Range Electrical Characteristics Capacitance Thermal Resistance Switching Characteristics Timing Diagrams Read Cycle Timing Write Cycle Timing Note: 23.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Read/Write Cycle Timing ZZ Mode Timing Page Ordering Information Package Diagrams A 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) Package Diagrams 0.900.05 51-85115-*B 0.56 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Package Diagrams 51-85180-*A SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) 1.40 MAX. 51-85180-*A Document History Page