Cypress CY7C1361C, CY7C1363C TAP Timing, Parameter Min Max Unit Clock, Output Times, Set-up Times

CY7C1361C

CY7C1363C

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in.

TAP Timing

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

12

Test Clock

(TCK)tTH

tTMSS tTMSH

Test Mode Select (TMS)

tTDIS tTDIH

Test Data-In (TDI)

3 4 5 6

tTL tCYC

tTDOV

tTDOX

	Test Data-Out
	(TDO)
	DON’T CARE	UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter	Parameter	Min.	Max.	Unit
Clock
tTCYC	TCK Clock Cycle Time	50		ns
tTF	TCK Clock Frequency		20	MHz
tTH	TCK Clock HIGH Time	20		ns
tTL	TCK Clock LOW Time	20		ns
Output Times
tTDOV	TCK Clock LOW to TDO Valid		10	ns
tTDOX	TCK Clock LOW to TDO Invalid	0		ns
Set-up Times
tTMSS	TMS Set-Up to TCK Clock Rise	5		ns
tTDIS	TDI Set-Up to TCK Clock Rise	5		ns
tCS	Capture Set-Up to TCK Rise	5		ns
Hold Times
tTMSH	TMS Hold after TCK Clock Rise	5		ns
tTDIH	TDI Hold after Clock Rise	5		ns
tCH	Capture Hold after Clock Rise	5		ns

Notes:

9.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

Document #: 38-05541 Rev. *F Page 14 of 31

[+] Feedback