Cypress CY7C1361C, CY7C1363C Logic Block Diagram CY7C1361C (256K x 36), Logic Block Diagram CY7C1363C (512K x 18)

CY7C1361C
CY7C1363C
Document #: 38-05541 Rev. *F Page 2 of 31
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
Q1
Q0
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
MEMORY
ARRAY
MODE A[1:0]
ZZ
DQ
s
DQP
A
DQP
B
DQP
C
DQP
D
A
0, A1, A
ADV
CLK
ADSP
ADSC
BWD
BWC
BWB
BWA
BWE
CE1
CE2
CE3
OE
GW
SLEEP
CONTROL
DQA , DQPA
BYTE
WRITE REGISTER
DQB
, DQPB
BYTE
WRITE REGISTER
DQC
, DQPC
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQ
D , DQP D
BYTE
WRITE REGISTER
DQ
D , DQP D
BYTE
WRITE REGISTER
DQC
, DQPC
BYTE
WRITE REGISTER
DQB
, DQPB
BYTE
WRITE REGISTER
DQA
, DQPA
BYTE
WRITE REGISTER
Logic Block Diagram – CY7C1361C (256K x 36)
ADDRESS
REGISTER
ADV
CLK BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
CE 1
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
OUTPUT
BUFFERS
INPUT
REGISTERS
MODE
CE2
CE3
GW
BWE
A
0,A1,A
BWB
BWA
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
A[1:0]
DQs
DQP
A
DQP
B
DQB,DQPB
WRITE DRIVER
DQA,DQPA
WRITE DRIVER
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1363C (512K x 18)
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