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Cypress CY7C1361C Timing Diagrams, Read Cycle Timing22, Adsc Address, Gw, Bwe,Bwx, DON’T Care

Models: CY7C1363C CY7C1361C

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CY7C1361C

CY7C1363C

Timing Diagrams

Read Cycle Timing[22]

tCYC

CLK

t CH

tADS tADH

t CL

ADSP

tADS tADH

ADSC

ADDRESS

tAS tAH

t WES tWEH

GW, BWE,BWX

tCES tCEH

Deselect Cycle

t ADVS tADVH

ADV
OE
		tOEV
		tOEHZ
		tCLZ
Data Out (Q)	High-Z	Q(A1)

tCDV

Single READ

ADV suspends burst

tOELZ	tCDV
	tCHZ
	tDOH

Q(A2)	Q(A2 + 1)	Q(A2 + 2)	Q(A2 + 3)	Q(A2)	Q(A2 + 1)	Q(A2 + 2)
				Burst wraps around
		BURST		to its initial state
		BURST
		READ

DON’T CARE

UNDEFINED

Note:

22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05541 Rev. *F

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Cypress CY7C1361C, CY7C1363C manual Timing Diagrams, Read Cycle Timing22, Adsc Address, Gw, Bwe,Bwx, DON’T Care

Contents

133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description1 Cypress Semiconductor Corporation Logic Block Diagram CY7C1361C 256K x Logic Block Diagram CY7C1363C 512K x CY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1363C Pin Configurations Ball BGA Pinout 2 Chip Enables with Jtag CLK Pin Configurations Ball Fbga Pinout 3 Chip EnableBWE Adsc ADV DQP B Power supply for the I/O circuitry Power supply inputs to the core of the deviceName Description Ground for the core of the device Pin DefinitionsGround for the I/O circuitry Burst Sequences Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Address Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description Used Function CY7C1361C Partial Truth Table for Read/Write3Truth Table for Read/Write3 Function CY7C1363C TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction Set Output Times TAP TimingParameter Min Max Unit Clock Set-up Times 5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Identification Register Definitions Register Name Bit Size x Scan Register SizesIdentification Codes Instruction Code Description Ball BGA Boundary Scan Order CY7C1361C 256K x Bit # Ball ID SignalCY7C1363C 512K x Bit # Ball ID Signal Name Name CY7C1361C 256K x Bit # Ball ID Signal Name Ball Fbga Boundary Scan Order Operating Range Electrical Characteristics Over the Operating Range 13Maximum Ratings Ambient Range AC Test Loads and Waveforms Capacitance15Thermal Resistance 3V I/O Test Load Switching Characteristics Over the Operating Range20 133 100 Parameter Description Unit Min Max Adsc Address Timing DiagramsRead Cycle Timing22 GW, BWE,BWX Write Cycle Timing22 DON’T Care Read/Write Cycle Timing22, 24 Burst Read DON’T Care Undefined ZZ Mode Timing26 Ordering Information Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCChip Enable CY7C1363C-133AXI CY7C1361C-133AJXI CY7C1361C-133AXC CY7C1361C-100AXC Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI CY7C1361C-100AXE Package Diagrams Pin Tqfp 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History