Cypress CY7C1363C, CY7C1361C manual Name Description, Power supply inputs to the core of the device

CY7C1361C

Pin Definitions

CY7C1363C

Name

I/O

Description

A0, A1, A

Input-

Address Inputs used to select one of the address locations. Sampled at the rising

Synchronous

edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE [2] are sampled

1

2

3

active. A[1:0] feed the 2-bit counter.

A,

B

Input-

Byte Write Select Inputs, active LOW. Qualified with

to conduct byte writes to the

BW

BW

BWE

BWC,BWD

Synchronous

SRAM. Sampled on the rising edge of CLK.

Input-

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a

GW

Synchronous

global write is conducted (ALL bytes are written, regardless of the values on

BW

X and BWE).

CLK

Input-

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment

Clock

the burst counter when ADV is asserted LOW, during a burst operation.

1

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

CE

Synchronous

conjunction with CE

and CE [2] to select/deselect the device. ADSP is ignored if

CE

1

is

2

3

HIGH. CE1 is sampled only when a new external address is loaded.

CE2

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

Synchronous

conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only when

a new external address is loaded.

3[2]

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

CE

Synchronous

conjunction with CE1 and CE2 to select/deselect the device.CE3 is sampled only when a

new external address is loaded.

Input-

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.

OE

Asynchronous

When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are

tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle

when emerging from a deselected state.

Input-

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automat-

ADV

Synchronous

ically increments the address in a burst cycle.

Input-

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.

ADSP

Synchronous

When asserted LOW, addresses presented to the device are captured in the address

registers. A[1:0]

are also loaded into the burst counter. When ADSP and ADSC are both

asserted, only ADSP is recognized. ASDP is ignored when

CE

1 is deasserted HIGH.

Input-

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.

ADSC

Synchronous

When asserted LOW, addresses presented to the device are captured in the address

registers. A[1:0]

are also loaded into the burst counter. When ADSP and ADSC are both

asserted, only ADSP is recognized.

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal

BWE

Synchronous

must be asserted LOW to conduct a byte write.

ZZ

Input-

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a

Asynchronous

non-time-critical “sleep” condition with data integrity preserved. For normal operation,

this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

DQs

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

Synchronous

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the previous clock rise of

the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,

the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state

condition.The outputs are automatically tri-stated during the data portion of a write

sequence, during the first clock when emerging from a deselected state, and when the

device is deselected, regardless of the state of

OE.

DQPX

I/O-

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs.

Synchronous

During write sequences, DQPX is controlled by BWX correspondingly.

MODE

Input-

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD

Static

or left floating selects interleaved burst sequence. This is a strap pin and should remain

static during device operation. Mode Pin has an internal pull-up.

VDD

Power Supply

Power supply inputs to the core of the device.

VDDQ

I/O Power Supply

Power supply for the I/O circuitry.

Document #: 38-05541 Rev. *F

Page 7 of 31

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