CY7C1361C
CY7C1363C
3.3V TAP AC Test Conditions
Input pulse levels | VSS to 3.3V |
Input rise and fall times | 1 ns |
Input timing reference levels | 1.5V |
Output reference levels | 1.5V |
Test load termination supply voltage | 1.5V |
2.5V TAP AC Test Conditions
Input pulse levels | VSS to 2.5V |
Input rise and fall time | 1 ns |
Input timing reference levels | 1.25V |
Output reference levels | 1.25V |
Test load termination supply voltage | 1.25V |
3.3V TAP AC Output Load Equivalent | 2.5V TAP AC Output Load Equivalent |
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| 1.5V |
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| 1.25V |
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| 50Ω |
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| 50Ω |
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TDO |
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| TDO |
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| ZO= 50Ω |
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| 20pF |
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| ZO= 50Ω |
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| 20pF |
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TAP DC Electrical Characteristics And Operating Conditions |
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(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[11] |
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Parameter |
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| Description |
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| Description |
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| Conditions |
| Min. |
| Max. | Unit | |||||||||||
VOH1 |
| Output HIGH Voltage |
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| IOH = |
| VDDQ = 3.3V |
| 2.4 |
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| V | |||||||||||
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| IOH = |
| VDDQ = 2.5V |
| 2.0 |
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| V | |||||||
VOH2 |
| Output HIGH Voltage |
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| IOH = |
| VDDQ = 3.3V |
| 2.9 |
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| V | |||||||||||
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| VDDQ = 2.5V |
| 2.1 |
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| V | |||||||
VOL1 |
| Output LOW Voltage |
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| IOL = 8.0 mA |
| VDDQ = 3.3V |
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| 0.4 | V | ||||||||
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| IOL = 8.0 mA |
| VDDQ = 2.5V |
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| 0.4 | V | ||||
VOL2 |
| Output LOW Voltage |
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| IOL = 100 µA |
| VDDQ = 3.3V |
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| 0.2 | V | ||||||||
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| VDDQ = 2.5V |
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| 0.2 | V | ||||
VIH |
| Input HIGH Voltage |
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| VDDQ = 3.3V |
| 2.0 |
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| VDD + 0.3 | V | |||||||||||
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| VDDQ = 2.5V |
| 1.7 |
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| VDD + 0.3 | V | |||||||
VIL |
| Input LOW Voltage |
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| VDDQ = 3.3V |
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| 0.7 | V | |||||||||||||||
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| VDDQ = 2.5V |
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| 0.7 | V | |||||||||||
IX |
| Input Load Current |
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| GND < VIN < VDDQ |
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| 5 | µA | |||||||||||
Identification Register Definitions
Instruction Field | CY7C1361C | CY7C1363C | Description |
(256K x36) | (512K x18) | ||
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Revision Number (31:29) | 000 | 000 | Describes the version number. |
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Device Depth (28:24)[12] | 01011 | 01011 | Reserved for Internal Use |
Device Width (23:18) | 101001 | 101001 | Defines memory type and architecture |
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Device Width (23:18) | 000001 | 000001 | Defines memory type and architecture |
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Cypress Device ID (17:12) | 100110 | 010110 | Defines width and density |
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Cypress JEDEC ID Code (11:1) | 00000110100 | 00000110100 | Allows unique identification of SRAM vendor. |
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ID Register Presence Indicator (0) | 1 | 1 | Indicates the presence of an ID register. |
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Notes:
11.All voltages referenced to VSS (GND).
12.Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: | Page 15 of 31 |
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