Cypress CY7C1363C, CY7C1361C manual Switching Characteristics Over the Operating Range20

CY7C1361C

CY7C1363C

Switching Characteristics Over the Operating Range[20, 21]

–133

–100

Parameter

Description

Unit

Min.

Max.

Min.

Max.

tPOWER

VDD(Typical) to the first Access[16]

1

1

ms

Clock

tCYC

Clock Cycle Time

7.5

10

ns

tCH

Clock HIGH

3.0

4.0

ns

tCL

Clock LOW

3.0

4.0

ns

Output Times

tCDV

Data Output Valid After CLK Rise

6.5

8.5

ns

tDOH

Data Output Hold After CLK Rise

2.0

2.0

ns

t

Clock to Low-Z[17, 18, 19]

0

0

ns

CLZ

t

Clock to High-Z[17, 18, 19]

3.5

3.5

ns

CHZ

tOEV

LOW to Output Valid

3.5

3.5

ns

OE

t

LOW to Output Low-Z[17, 18, 19]

0

0

ns

OE

OELZ

tOEHZ

HIGH to Output High-Z[17, 18, 19]

3.5

3.5

ns

OE

Set-up Times

tAS

Address Set-up Before CLK Rise

1.5

1.5

ns

tADS

Set-up Before CLK Rise

1.5

1.5

ns

ADSP,

ADSC

tADVS

Set-up Before CLK Rise

1.5

1.5

ns

ADV

tWES

[A:D] Set-up Before CLK Rise

1.5

1.5

ns

GW,

BWE,

BW

tDS

Data Input Set-up Before CLK Rise

1.5

1.5

ns

tCES

Chip Enable Set-up

1.5

1.5

ns

Hold Times

tAH

Address Hold After CLK Rise

0.5

0.5

ns

tADH

Hold After CLK Rise

0.5

0.5

ns

ADSP,

ADSC

tWEH

[A:D] Hold After CLK Rise

0.5

0.5

ns

GW,

BWE,

BW

tADVH

Hold After CLK Rise

0.5

0.5

ns

ADV

tDH

Data Input Hold After CLK Rise

0.5

0.5

ns

tCEH

Chip Enable Hold After CLK Rise

0.5

0.5

ns

Notes:

16.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a read or write operation can be initiated.

17.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

18.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

19.This parameter is sampled and not 100% tested.

20.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

21.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05541 Rev. *F Page 21 of 31

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