Manuals / Cypress / Computer Equipment / Computer Hardware

Cypress CY7C1361C, CY7C1363C manual Read/Write Cycle Timing22, 24, Burst Read DON’T Care Undefined

Models: CY7C1363C CY7C1361C

1 31

Download 31 pages 44.93 Kb

Page 24

Image 24

CY7C1361C

CY7C1363C

Timing Diagrams (continued)

Read/Write Cycle Timing[22, 24, 25]

tCYC

CLK

tt

CH CL

tADS tADH

ADSP

ADSC

tAS tAH

ADDRESS	A1	A2	A3		A4
				tWES	tWEH
BWE, BWX
		tCES tCEH
CE
ADV
OE
				tDS	tDH
					tOELZ
Data In (D)		High-Z	t	D(A3)
			OEHZ		tCDV
					tCDV
Data Out (Q)		Q(A1)	Q(A2)		Q(A4)	Q(A4+1)	Q(A4+2)	Q(A4+3)
		Back-to-Back READs		Single WRITE		BURST READ
					DON’T CARE	UNDEFINED

Notes:

24.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

25.GW is HIGH.

A5 A6

D(A5) D(A6)

Back-to-Back

WRITEs

Document #: 38-05541 Rev. *F

Page 24 of 31

[+] Feedback

Image 24

Cypress CY7C1361C, CY7C1363C manual Read/Write Cycle Timing22, 24, Burst Read DON’T Care Undefined

Contents

Features Selection Guide Functional Description1133 MHz 100 MHz Unit Cypress Semiconductor Corporation Logic Block Diagram CY7C1361C 256K x Logic Block Diagram CY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a version CY7C1361C 256K xCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1363C Pin Configurations Ball BGA Pinout 2 Chip Enables with Jtag Pin Configurations Ball Fbga Pinout 3 Chip Enable BWE Adsc ADVCLK DQP B Power supply inputs to the core of the device Power supply for the I/O circuitryName Description Pin Definitions Ground for the core of the deviceGround for the I/O circuitry Interleaved Burst Address Table Mode = Floating or VDD Functional OverviewBurst Sequences Address ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitAddress Cycle Description Used Partial Truth Table for Read/Write3 Truth Table for Read/Write3Function CY7C1361C Function CY7C1363C TAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction Set TAP Timing Parameter Min Max Unit ClockOutput Times Set-up Times TAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register Definitions Scan Register Sizes Identification CodesRegister Name Bit Size x Instruction Code Description CY7C1361C 256K x Bit # Ball ID Signal CY7C1363C 512K x Bit # Ball ID Signal NameBall BGA Boundary Scan Order Name CY7C1361C 256K x Bit # Ball ID Signal Name Ball Fbga Boundary Scan Order Electrical Characteristics Over the Operating Range 13 Maximum RatingsOperating Range Ambient Range Capacitance15 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test Load Switching Characteristics Over the Operating Range20 133 100 Parameter Description Unit Min Max Timing Diagrams Read Cycle Timing22Adsc Address GW, BWE,BWX Write Cycle Timing22 DON’T Care Read/Write Cycle Timing22, 24 Burst Read DON’T Care Undefined ZZ Mode Timing26 Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXC Chip Enable CY7C1363C-133AXI CY7C1361C-133AJXIOrdering Information CY7C1361C-133AXC Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXC Chip Enable CY7C1363C-100AXI CY7C1361C-100AJXICY7C1361C-100AXC CY7C1361C-100AXE Package Diagrams Pin Tqfp 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History