Scan Register Sizes, Identification Codes | Cypress CY7C1361C

				CY7C1361C
				CY7C1363C
				CY7C1363C


Scan Register Sizes

Register Name			Bit Size (x 36)	Bit Size (x 18)

Instruction			3	3

Bypass			1	1

ID			32	32

Boundary Scan Order (119-ball BGA package)			71	71

Boundary Scan Order (165-ball FBGA package)			71	71

Identification Codes

Instruction	Code	Description
EXTEST	000	Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
		Forces all SRAM outputs to High-Z state.
IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO.
		This operation does not affect SRAM operations.
SAMPLE Z	010	Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
		Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
		Does not affect SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operations.

Document #: 38-05541 Rev. *F

Page 16 of 31

[+] Feedback

Image 16

Cypress CY7C1361C manual Scan Register Sizes, Identification Codes, Register Name Bit Size x, Instruction Code Description

Contents

Features Selection Guide Functional Description1133 MHz 100 MHz Unit Cypress Semiconductor Corporation Logic Block Diagram CY7C1361C 256K x Logic Block Diagram CY7C1363C 512K x CY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1363C Pin Configurations Ball BGA Pinout 2 Chip Enables with Jtag Pin Configurations Ball Fbga Pinout 3 Chip Enable BWE Adsc ADVCLK DQP B Power supply for the I/O circuitry Power supply inputs to the core of the deviceName Description Ground for the core of the device Pin DefinitionsGround for the I/O circuitry Interleaved Burst Address Table Mode = Floating or VDD Functional OverviewBurst Sequences Address Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description Used Partial Truth Table for Read/Write3 Truth Table for Read/Write3Function CY7C1361C Function CY7C1363C TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction Set TAP Timing Parameter Min Max Unit ClockOutput Times Set-up Times TAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register Definitions Scan Register Sizes Identification CodesRegister Name Bit Size x Instruction Code Description CY7C1361C 256K x Bit # Ball ID Signal CY7C1363C 512K x Bit # Ball ID Signal NameBall BGA Boundary Scan Order Name CY7C1361C 256K x Bit # Ball ID Signal Name Ball Fbga Boundary Scan Order Electrical Characteristics Over the Operating Range 13 Maximum RatingsOperating Range Ambient Range Capacitance15 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test Load Switching Characteristics Over the Operating Range20 133 100 Parameter Description Unit Min Max Timing Diagrams Read Cycle Timing22Adsc Address GW, BWE,BWX Write Cycle Timing22 DON’T Care Read/Write Cycle Timing22, 24 Burst Read DON’T Care Undefined ZZ Mode Timing26 Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXC Chip Enable CY7C1363C-133AXI CY7C1361C-133AJXIOrdering Information CY7C1361C-133AXC Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXC Chip Enable CY7C1363C-100AXI CY7C1361C-100AJXICY7C1361C-100AXC CY7C1361C-100AXE Package Diagrams Pin Tqfp 14 x 20 x 1.4 mm Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History