ZZ Mode Timing26 | Cypress CY7C1363C, CY7C1361C manual

CY7C1361C

CY7C1363C

Timing Diagrams (continued)

ZZMode Timing[26, 27]

CLK

tZZ

tZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

Outputs (Q)

High-Z

DON’T CARE

tZZREC

tRZZI

DESELECT or READ Only

Notes:

26.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

27.DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05541 Rev. *F

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Cypress CY7C1363C, CY7C1361C manual ZZ Mode Timing26

Contents

Selection Guide Functional Description1 Features133 MHz 100 MHz Unit Cypress Semiconductor Corporation Logic Block Diagram CY7C1363C 512K x Logic Block Diagram CY7C1361C 256K x CY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1363C 512K x CY7C1363C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version Pin Configurations Ball BGA Pinout 2 Chip Enables with Jtag BWE Adsc ADV Pin Configurations Ball Fbga Pinout 3 Chip EnableCLK DQP B Power supply for the I/O circuitry Power supply inputs to the core of the deviceName Description Ground for the core of the device Pin DefinitionsGround for the I/O circuitry Functional Overview Interleaved Burst Address Table Mode = Floating or VDDBurst Sequences Address Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description Used Truth Table for Read/Write3 Partial Truth Table for Read/Write3Function CY7C1361C Function CY7C1363C TAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass Register Parameter Min Max Unit Clock TAP TimingOutput Times Set-up Times 3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register Definitions Identification Codes Scan Register SizesRegister Name Bit Size x Instruction Code Description CY7C1363C 512K x Bit # Ball ID Signal Name CY7C1361C 256K x Bit # Ball ID SignalBall BGA Boundary Scan Order Name Ball Fbga Boundary Scan Order CY7C1361C 256K x Bit # Ball ID Signal Name Maximum Ratings Electrical Characteristics Over the Operating Range 13Operating Range Ambient Range Thermal Resistance Capacitance15AC Test Loads and Waveforms 3V I/O Test Load 133 100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range20 Read Cycle Timing22 Timing DiagramsAdsc Address GW, BWE,BWX DON’T Care Write Cycle Timing22 Burst Read DON’T Care Undefined Read/Write Cycle Timing22, 24 ZZ Mode Timing26 Chip Enable CY7C1363C-133AXI CY7C1361C-133AJXI Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCOrdering Information CY7C1361C-133AXC Chip Enable CY7C1363C-100AXI CY7C1361C-100AJXI Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCCY7C1361C-100AXC CY7C1361C-100AXE Pin Tqfp 14 x 20 x 1.4 mm Package Diagrams Ball BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change