Renesas R61509V manual

Contents

Main R61509V Page RAM Address and Display Position on the Panel.............................................. 129 Page Page Description Features R61509V Target Spec Power Supply Specifications Table 1 See DC characteristics in Chapter Electrical Characteristics for voltage spec. Difference Between R61509 and R61509V R61509V Target Spec Block Diagram Figure 1 Gamma generating circuit Grayscale voltage Block Function Page Page R61509V Target Spec Pin Function Table 5 External Power Supply Table 6 Bus Interface (Amplitude: IOVCC~GND) Page R61509V Target Spec Table 7 Internal Power Supply Circuit R61509V Target Spec Table 8 LCD drive Page R61509V Pad Arrangement Rev 0.6 BUMP 840um Chip Top View Page R61509V Pad Coordinate Unitm Page Page Page Page Page Page Page Page Page Page Page Page Page Page R61509V Target Spec Bump Arrangement Figure 3 R61509V Wiring Example & Recommended Wiring Resistance Chip BUMP Top View 840um GRAM Address Map Table 11 GRAM address and display position on the panel (SS = 0, BGR = 0) R61509V Target Spec Table 12 GRAM address and display position on the panel (SS = 1, BGR = 1) S2 S1 Instruction Page Page Page R61509V Target Spec ORG = 0 ORG = 1 Figure 4 Automatic Address Update Page R61509V Target Spec Display Control 2 (R008h) Page Page Page Page Page Page Page Page Page 0h Page Page Page Page R61509V Target Spec Page R61509V Target Spec Panel Interface Control 8 (R022h) 1) VEQW [2:0]=0h 2) VEQWI [2:0] 0h Figure 7 Page R61509V Target Spec Panel Interface Control 9 (R023h) Page Page R61509V Target Spec Page Page R61509V Target Spec VC[2:0]: Sets VCI voltage level. DC0 Value and DCDC1 Step-up Clock Signal Waveform Example DC1 Value and DCDC2 Step-up Clock Signal Waveform Example Page Page Page Page Page Page R61509V Target Spec Table 48 Page R61509V Target Spec Rev. 0.11 April 25, 2008, page 81 of 181 Figure 9 GRAM Address Map and Window Address Area R61509V Target Spec Control Control 1 ~ 14 (R300h to R309h) Page Page Page R61509V Target Spec Table 53 R61509V Target Spec Rev. 0.11 April 25, 2008, page 87 of 181 Table 54 R61509V Target Spec Page Page R61509V Target Spec R6F1h Write data to NVM (NVM) Read data from NVM R280h Write 1 to NVDAT[15]. R61509VInstruction List Rev 0.50 2008. 04. 22 Middle category 6F2h NVM Access Control 3 000000000000 502h RAM Address 2 (End Line Address) 401h Base Image Display Control Reset Function Page R61509V Target Spec Basic Mode Operation of the R61509V Figure 12 Reset state Display OFF VSYNC interface Interface and Data Format R61509V System Page System Interface R61509V Target Spec R61509V Figure 16 18-bit Interface Data Format (RAM Data Write / RAM Data Read) RAM data read 80-System 18-bit Bus Interface A1 HWR R61509V Figure 18 16-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read) 80-System 16-bit Bus Interface A1 HWR RS WR: R61509V Target Spec 1 Figure 20 16-bit Interface Data Format (RAM Data Read) DB 17 2 Page R61509V Target Spec R61509V Figure 23 9-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read) A1 HWR RS WR: HOST PROCESSOR R61509V Target Spec Figure 25 9-bit Data Transfer Synchronization UpperUpper Lower DB17 ~ DB9 R61509V IM[2:0] = 001 CSn (RDX(RDX D15-0 DB17-10 DB9-0 Figure 26 8-bit Interface Instruction write Device code read / Instruction read R61509V Target Spec RAM data write (2-transfer mode: TRI = 0) Figure 29 8-bit Interface Data Format (RAM Data Read) RAM data write (3-transfer mode: TRI = 1, DFM = 1) Figure 28 8-bit Interface Data Format (RAM Data Write) Page Page R61509V Target Spec RAM data write Figure 31 Serial Interface Data Format Instruction R61509V Target Spec (a) Clock synchronization serial data transfer (basic mode) Figure 32 Data Transfer in Serial Interface (b) Clock synchronization serial consecutive data transfer (c) RAM read data transfer VSYNC Interface R61509V HOST PROCESSOR fosc 1 )clocks(23)insargm)NL(esDisplayLin)BP(BackPorch( )NL(esDisplayLin240 ]Hz.)[(mineedRAMWriteSp + > R61509V Target Spec Main panel Figure 36 RAM Write Speed Margins Front porch (2 lines) Line processing R61509V Target Spec Figure 37 Sequences to Switch between VSYNC and Internal Clock Operation Modes Internal Clock Operation to VSYNC Interface VSYNC Interface to Internal Clock Operation Internal clock operation FMARK Interface R61509V Page Page R61509V Target Spec Table 60 Table 61 R61509V Target Spec FMP Setting Example Figure 41 RGB Interface Page Page Page Page R61509V Target Spec Figure 47 Example of 16-Bit RGB Interface and Data Format R61509V HOST PROCESSOR Data format for the16-bit interface (RIM = 1) HOST PROCESSOR R61509V Data format for the 18-bit interface (RIM = 0) Page RAM Address and Display Position on the Panel Restrictions in Setting Display Control Instruction R61509V Target Spec RAM line address Base image RAM area Partial image RAM area LCD panel physical line address R61509V Target Spec Figure 52 Full Screen Display (no Partial) RAM line address Base image display instruction BASEE 1 NL[5:0] 6h35 PTDE 0 LCD panel physical line address R61509V Target Spec Figure 53 Partial Display Base image (non-lit display) Window Address Function Window address area R61509V Target Spec Scan Mode Setting Figure 55 Interchanging forward direction (GS=0) Interchanging backward direction (GS=1) Left/right backward direction (GS=1) R G B LCD V0 B BSLBSM GRAM Page R61509V Target Spec Partial Display Function G41 G60 R61509V Target Spec Liquid Crystal Panel Interface Timing Figure 58 R61509V Target Spec RGB Interface Operation Figure 59 Page R61509V Target Spec Table 71 Reference Level Adjustment Registers and Resistors R61509V Target Spec Interpolation Registers Table 72 Interpolation Registers R61509V Target Spec Table 74 Interpolation Factor for V56 to V61 R61509V Target Spec Rev. 0.11 April 25, 2008, page 147 of 181 Table 75 Grayscale Voltage Calculation Formula Note: Make sure that V = VREG1OUT VGS SUMR = (R0R8) 70R. V63 0.2V R61509V Target Spec Frame Memory Data and the Grayscale Voltage Table 76 R61509V Target Spec Rev. 0.11 April 25, 2008, page 149 of 181 Power Supply Generating Circuit R61509V Figure 61 R61509V Target Spec Rev. 0.11 April 25, 2008, page 150 of 181 R61509V Figure 62 Specifications of Power-supply Circuit External Elements R61509V Target Spec Voltage Setting Pattern Diagram Figure 63 Page R61509V Target Spec VCOMH and VREG1OUT Voltage Adjustment Sequence Figure 65 Set write data. Complete the VCOMH level adjustment. NVM Control Page R61509V Target Spec Figure 67 NVM Write Sequence 150msr50ms(TBD) NVM Write Sequence NVM Load (Register Resetting) Sequence R61509V Target Spec Figure 68 NVM Erase Sequence NVM Erase Sequence Power supply OFF sequence Start of rasing End of erasing Power Supply Setting Sequence Figure 69 Transfer synchronization Power Supply ON Sequence (A) Liquid crystal power supply OFF (DCDC OFF) state Display OFF state Power Supply OFF Sequence Notes to Power Supply ON Sequence R61509V Target Spec Instruction Setting Sequence and Refresh Sequence Figure 71 R61509V Target Spec Shutdown Mode Sequences Figure 72 Data and RS = Dont care Display ON sequence R61509V Target Spec Figure 73 Display OFF sequence R61509V Target Spec Figure 74 Display OFF sequence (2) 9-/8-bit interface operation R61509V Target Spec 8-Color Mode Setting Figure 76 8-color mode display R00Bh: COL=1 Absolute Maximum Ratings Table 82 R61509V Target Spec Electrical Characteristics Page R61509V Target Spec Step-up Circuit Characteristics Table 84 Internal Reference Voltage: Condition (VCC= 2.50V~3.30V, Ta= -40C~+85C) Table 85 Page R61509V Target Spec R61509V Target Spec Clock Synchronous Serial Interface Timing Characteristics (IOVCC=1.65V~3.30V) TBD Table 90 RGB Interface Timing Characteristics (18-/16-bit RGB interface, IOVCC=1.65V~3.30V) TBD Table 91 R61509V Target Spec LCD Driver Output Characteristics Table 92 Reset Timing Characteristics Table 93IOVCC=1.65V3.30V R61509V Target Spec Figure 77 Page R61509V Target Spec Timing Characteristics 80-system Bus Interface DB17-0 Figure A 80-system Bus Interface R61509V Target Spec CSX SCL SDO SDI Figure B Clock Synchronous Serial Interface Timing Reset Operation ENABLE RGB Interface DB17-0 DOTCLK VSYNCX HSYNCX http://www.renesas.com RENESAS SALES OFFICES Colophon .1.0 Revision Record