Renesas manual R61509V Instruction List Rev 0.50 2008

●R61509V Instruction List						Rev 0.50 2008. 04. 22
Major category		Middle category		Minor category				Upper Code								Lower Code
Upper Index			Index	Command	IB15	IB14	IB13	IB12	IB11	IB10	IB9	IB8	IB7	IB6	IB5	IB4	IB3	IB2	IB1	IB0
-	Index		－	Index	0	0	0	0	0	ID10	ID9	ID8	ID7	ID6	ID5	ID4	ID3	ID2	ID21	ID0
0**	Display Control	00*	000h	Device Code Read	ALMID1[7] ALMID1[6] ALMID1[5] ALMID1[4] ALMID1[3]					ALMID1[2]	ALMID1[1]	ALMID1[0]	ALMID0[7]	ALMID0[6]	ALMID0[5]	ALMID0[4]	ALMID0[3]	ALMID0[2]	ALMID0[1]	ALMID0[0]
					(1)	(0)	(1)	(1)	(0)	(1)	(0)	(1)	(0)	(0)	(0)	(0)	(1)	(0)	(0)	(1)
		Display Control	001h	Driver Output Control	0	0	0	0	0	SM	0	SS	0	0	0	0	0	0	0	0
		in general								(0)		(0)
			002h	LCD Drive Waveform Control	0	0	0	0	0	0	0	BC	0	0	0	0	0	0	0	0
												(0)
			003h	Entry Mode	TRI	DFM	0	BGR	0	0	0	0	ORG	0	ID[1]	ID[0]	AM	0	0	0
					(0)	(0)		(0)					(0)		(1)	(1)	(0)
			004h	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
			005h	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
			006h	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
			007h	Display Control 1	0	0	0	PTDE	0	0	0	BASEE	0	0	0	0	0	0	0	0
								(0)				(0)
			008h	Display Control 2	FP[7]	FP[6]	FP[5]	FP[4]	FP[3]	FP[2]	FP[1]	FP[0]	BP[7]	BP[6]	BP[5]	BP[4]	BP[3]	BP[2]	BP[1]	BP[0]
					(0)	(0)	(0)	(0)	(1)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(1)	(0)	(0)	(0)
			009h	Display Control 3	0	0	0	0	PTV	PTS	0	0	0	0	0	0	0	0	0	0
									(0)	(0)
			00Ah	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
			00Bh	8 Color Control	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	COL
																				(0)
			00Ch	External Display Interface Control	0	ENC[2]	ENC[1]	ENC[0]	0	0	0	RM	0	0	DM[1]	DM[0]	0	0	0	RIM
				1		(0)	(0)	(0)				(0)			(0)	(0)				(0)
			00D-00Eh	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
			00Fh	External Display Interface Control	0	0	0	0	0	0	0	0	0	0	0	VSPL	HSPL	0	EPL	DPL
				2												(0)	(0)		(0)	(0)

		01*	010h	Panel Interface Control 1	0	0	0	0	0	0	DIVI[1]	DIVI[0]	0	0	0	RTNI[4]	RTNI[3]	RTNI[2]	RTNI[1]	RTNI[0]
											(0)	(0)				(1)	(1)	(0)	(0)	(1)
		Panel Interface	011h	Panel Interface Control 2	0	0	0	0	0	NOWI[2]	NOWI[1]	NOWI[0]	0	0	0	0	0	SDTI[2]	SDTI[1]	SDTI[0]
		(Internal Clock)								(0)	(0)	(1)						(0)	(0)	(1)
			012h	Panel Interface Control 3	0	0	0	0	0	VEQWI[2]	VEQWI[1]	VEQWI[0]	0	0	0	0	0	SEQWI[2]	SEQWI[1]	SEQWI[0]
										(0)	(0)	(0)						(0)	(0)	(0)
			013h	Panel Interface Control 4	0	0	0	0	0	0	0	0	0	0	0	0	0	MCPI[2]	MCPI[1]	MCPI[0]
																		(0)	(0)	(1)
			014h	Panel Interface Control 5	0	0	0	0	0	0	0	0	0	PCDIVH[2]	PCDIVH[1]	PCDIVH[0]	0	PCDIVL[2]	PCDIVL[1]	PCDIVL[0]
														(1)	(0)	(1)		(1)	(0)	(1)
			014-01Fh	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
		02*	020h	Panel Interface Control 6	0	0	0	0	0	0	DIVE[1]	DIVE[0]	0	0	0	RTNE[4]	RTNE[3]	RTNE[2]	RTNE[1]	RTNE[0]
											(0)	(0)				(1)	(1)	(0)	(0)	(1)
		Panel Interface	021h	Panel Interface Control 7	0	0	0	0	0	NOWE[2]	NOWE[1]	NOWE[0]	0	0	0	0	0	SDTE[2]	SDTE[1]	SDTE[0]
		(External Clock)								(0)	(0)	(1)						(0)	(0)	(1)
			022h	Panel Interface Control 8	0	0	0	0	0	VEQWE[2]	VEQWE[1]	VEQWE[0]	0	0	0	0	0	SEQWE[2]	SEQWE[1]	SEQWE[0]
										(0)	(0)	(0)						(0)	(0)	(0)
			023h	Panel Interface Control 9	0	0	0	0	0	0	0	0	0	0	0	0	0	MCPE[2]	MCPE[1]	MCPE[0]
																		(0)	(0)	(1)
			024h-08Fh	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
		09*	090h	Frame Marker Control	FMKM	FMI[2]	FMI[1]	FMI[0]	0	0	0	FMP[8]	FMP[7]	FMP[6]	FMP[5]	FMP[4]	FMP[3]	FMP[2]	FMP[1]	FMP[0]
					(0)	(0)	(0)	(0)				(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
		Frame Marker Control	091-0FFh	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
1**	Power Control		100h	Power Control 1	0	0	0	0	0	BT[2]	BT[1]	BT[0]	0	0	AP[1]	AP[0]	0	DSTB	0	0
										(0)	(1)	(1)			(1)	(1)		(0)
			101h	Power Control 2	0	0	0	0	0	DC1[2]	DC1[1]	DC1[0]	0	DC0[2]	DC0[1]	DC0[0]	0	VC[2]	VC[1]	VC[0]
										(0)	(1)	(0)		(1)	(0)	(0)		(1)	(1)	(1)
			102h	Power Control 3	VRH[4]	VRH[3]	VRH[2]	VRH[1]	VRH[0]	0	0	VCMR	1	0	PSON	PON	0	0	0	0
					(0)	(0)	(0)	(0)	(0)			(1)			(0)	(0)
			103h	Power Control 4	0	0	0	VDV[4]	VDV[3]	VDV[2]	VDV[1]	VDV[0]	0	0	0	0	0	0	0	0
								(0)	(0)	(0)	(0)	(0)
			104-1FFh	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
2**	RAM Access	20*	200h	RAM Address Set	0	0	0	0	0	0	0	0	AD[7]	AD[6]	AD[5]	AD[4]	AD[3]	AD[2]	AD[1]	AD[0]
				(Horizontal Address)									(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
		RAM Read/Write	201h	RAM Address Set	0	0	0	0	0	0	0	AD[16]	AD[15]	AD[14]	AD[13]	AD[12]	AD[11]	AD[10]	AD[9]	AD[8]
				(Vertical Address)								(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
			202h	GRAM Data Write/GRAM Data				RAM write data WD[17:0] / RAM read data RD [17:0] is transferred via different data bus in different interface operation.
				Read
			203-20Fh	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
		21*	210h	Window Horizontal RAM Address	0	0	0	0	0	0	0	0	HSA[7]	HSA[6]	HSA[5]	HSA[4]	HSA[3]	HSA[2]	HSA[1]	HSA[0]
				Start									(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
		Window Address	211h	Window Horizontal RAM Address	0	0	0	0	0	0	0	0	HEA[7]	HEA[6]	HEA[5]	HEA[4]	HEA[3]	HEA[2]	HEA[1]	HEA[0]
				End									(1)	(1)	(1)	(0)	(1)	(1)	(1)	(1)
			212h	Window Vertical RAM Address	0	0	0	0	0	0	0	VSA[8]	VSA[7]	VSA[6]	VSA[5]	VSA[4]	VSA[3]	VSA[2]	VSA[1]	VSA[0]
				Start								(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
			213h	Window Vertical RAM Address End	0	0	0	0	0	0	0	VEA[8]	VEA[7]	VEA[6]	VEA[5]	VEA[4]	VEA[3]	VEA[2]	VEA[1]	VEA[0]
												(1)	(1)	(0)	(1)	(0)	(1)	(1)	(1)	(1)
			214-27Fh	Setting inhibited
		28*	280h	NVM Data Read / NVM Data Write	1	VCM[6]	VCM[5]	VCM[4]	VCM[3]	VCM[2]	VCM[1]	VCM[0]	UID[7]	UID[6]	UID[5]	UID[4]	UID[3]	UID[2]	UID[1]	UID[0]
						(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)	(1)
			281-2FFh	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
3**	Gamma Control	30*	300h	Gamma Control (1)	0	0	0	PR0P01[4]	PR0P01[3]	PR0P01[2]	PR0P01[1]	PR0P01[0]	0	0	0	PR0P00[4]	PR0P00[3]	PR0P00[2]	PR0P00[1]	PR0P00[0]
								(0)	(0)	(0)	(0)	(0)				(0)	(0)	(0)	(0)	(0)
		Gamma Control	301h	Gamma Control (2)	PR0P04[3]	PR0P04[2]	PR0P04[1]	PR0P04[0]	PR0P03[3]	PR0P03[2]	PR0P03[1]	PR0P03[0]	0	0	0	PR0P02[4]	PR0P02[3]	PR0P02[2]	PR0P02[1]	PR0P02[0]
					(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)				(0)	(0)	(0)	(0)	(0)
			302h	Gamma Control (3)	0	0	0	PR0P06[4]	PR0P06[3]	PR0P06[2]	PR0P06[1]	PR0P06[0]	0	0	0	0	PR0P05[3]	PR0P05[2]	PR0P05[1]	PR0P05[0]
								(0)	(0)	(0)	(0)	(0)					(0)	(0)	(0)	(0)
			303h	Gamma Control (4)	0	0	0	PR0P08[4]	PR0P08[3]	PR0P08[2]	PR0P08[1]	PR0P08[0]	0	0	0	PR0P07[4]	PR0P07[3]	PR0P07[2]	PR0P07[1]	PR0P07[0]
								(0)	(0)	(0)	(0)	(0)				(0)	(0)	(0)	(0)	(0)
			304h	Gamma Control (5)	0	0	PI0P3[1]	PI0P3[0]	0	0	PI0P2[1]	PI0P2[0]	0	0	PI0P1[1]	PI0P1[0]	0	0	PI0P0[1]	PI0P0[0]
							(0)	(0)			(0)	(0)			(0)	(0)			(0)	(0)
			305h	Gamma Control (6)	0	0	0	PR0N01[4]	PR0N01[3]	PR0N01[2]	PR0N01[1]	PR0N01[0]	0	0	0	PR0N00[4]	PR0N00[3]	PR0N00[2]	PR0N00[1]	PR0N00[0]
								(0)	(0)	(0)	(0)	(0)				(0)	(0)	(0)	(0)	(0)
			306h	Gamma Control (7)	PR0N04[3]	PR0N04[2]	PR0N04[1]	PR0N04[0]	PR0N03[3]	PR0N03[2]	PR0N03[1]	PR0N03[0]	0	0	0	PR0N02[4]	PR0N02[3]	PR0N02[2]	PR0N02[1]	PR0N02[0]
					(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)				(0)	(0)	(0)	(0)	(0)
			307h	Gamma Control (8)	0	0	0	PR0N06[4]	PR0N06[3]	PR0N06[2]	PR0N06[1]	PR0N06[0]	0	0	0	0	PR0N05[3]	PR0N05[2]	PR0N05[1]	PR0N05[0]
								(0)	(0)	(0)	(0)	(0)					(0)	(0)	(0)	(0)
			308h	Gamma Control (9)	0	0	0	PR0N08[4]	PR0N08[3]	PR0N08[2]	PR0N08[1]	PR0N08[0]	0	0	0	PR0N07[4]	PR0N07[3]	PR0N07[2]	PR0N07[1]	PR0N07[0]
								(0)	(0)	(0)	(0)	(0)				(0)	(0)	(0)	(0)	(0)
			309h	Gamma Control (10)	0	0	PI0N3[1]	PI0N3[0]	0	0	PI0N2[1]	PI0N2[0]	0	0	PI0N1[1]	PI0N1[0]	0	0	PI0N0[1]	PI0N0[0]
							(0)	(0)			(0)	(0)			(0)	(0)			(0)	(0)
			30Ah-3FFh	Setting inhibited
4**	Base Image Display Control		400ｈ	Base Image Number of Line	GS	NL[5]	NL[4]	NL[3]	NL[2]	NL[1]	NL[0]	0	0	SCN[5]	SCN[4]	SCN[3]	SCN[2]	SCN[1]	SCN[0]	0
					(0)	(1)	(1)	(0)	(1)	(0)	(1)			(0)	(0)	(0)	(0)	(0)	(0)
			401h	Base Image Display Control	0	0	0	0	0	0	0	0	0	0	0	0	0	NDL	VLE	REV
																		(0)	(0)	(0)
			402h-403h	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
			404h	Base Image Vertical Scroll Control	0	0	0	0	0	0	0	VL[8]	VL[7]	VL[6]	VL[5]	VL[4]	VL[3]	VL[2]	VL[1]	VL[0]
												(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
			405-4FFh	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
5**	Partial Display Control		500h	Partial Image 1: Display Position	0	0	0	0	0	0	0	PTDP[8]	PTDP[7]	PTDP[6]	PTDP[5]	PTDP[4]	PTDP[3]	PTDP[2]	PTDP[1]	PTDP[0]
												(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
			501h	RAM Address 1 (Start Line	0	0	0	0	0	0	0	PTSA[8]	PTSA[7]	PTSA[6]	PTSA[5]	PTSA[4]	PTSA[3]	PTSA[2]	PTSA[1]	PTSA[0]
				Address)								(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
			502h	RAM Address 2 (End Line Address)	0	0	0	0	0	0	0	PTEA[8]	PTEA[7]	PTEA[6]	PTEA[5]	PTEA[4]	PTEA[3]	PTEA[2]	PTEA[1]	PTEA[0]
												(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
			503h-5FFh	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
6**	Pin Control	60*	600h	Test Register (Software Reset)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	TRSR
																				(0)
			601-6EFh	Setting inhibited	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
		6F*	6F0h	NVM Access Control 1	0	0	0	0	0	0	0	0	TE	CALB	EOP[1]	EOP[0]	0	0	0	0
													(0)	(0)	(0)	(0)
			6F1h	NVM Access Control 2	NVDAT[15] NVDAT[14] NVDAT[13] NVDAT[12] NVDAT[11] NVDAT[10] NVDAT[9] NVDAT[8] NVDAT[7] NVDAT[6] NVDAT[5] NVDAT[4] NVDAT[3] NVDAT[2] NVDAT[1] NVDAT[0]
					(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)	(0)
			6F2h	NVM Access Control 3	0	0	0	0	0	0	0	0	0	0	0	0	NVVRF	0	0	0
																	(0)
		NVM-I/F	6F3-FFFh	Setting inhibited

Note 1: Values in parentheses ( ) are default values.

Note 2: Do not access instructions that are not shown in the above table.

Note

-

Device Code "B509h"

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-