R61509VTarget Spec

Pin Function

Table 5 External Power Supply

Signal

I/O

Connect to

Function

When not

used

 

 

 

 

 

 

 

 

 

VCC

I

Power

Power supply for Internal VDD regulator.

―

supply

≧

 

 

 

VCC IOVCC

 

IOVCC

I

Power

Power supply for interface pins.

―

supply

 

 

 

 

GND

I

Power

GND level for internal logic and interface pins. GND=0V.

―

supply

 

 

 

 

VCI

I

Power

Power supply for liquid crystal power supply analog circuit.

―

supply

 

 

 

 

 

 

Reference

Connect to an external power supply at the same level as VCI the

 

VCILVL

I

power

power supply for liquid crystal power supply analog circuit. In case of

―

 

 

supply

COG, connect to VCI on the FPC to prevent noise.

 

 

 

Power

Analog GND (for logic regulator and liquid crystal power supply).

 

AGND

I

AGND = 0V.

―

supply

 

 

In case of COG, connect to GND on the FPC to prevent noise.

 

 

 

 

 

 

 

 

 

 

VPP1

I

Power

Power supply for internal NVM.

Open or

supply

AGND

 

 

See section “NVM Control” for input voltages during write and erase

 

 

Power

Open or

VPP3A

I

operation using VPP1-VPP3A pins.

supply

AGND

 

 

 

Note 1: VCC, GND and AGND pins are allocated several different places on the chip. Make sure to connect all of them to power following “Connection Example”.

Table 6 Bus Interface (Amplitude: IOVCC~GND)

 

Signal

I/O

Connect to

 

 

Function

When not

 

 

 

used

 

 

 

 

 

 

 

 

 

 

Host

Chip selection signal. (Amplitude: IOVCC-GND)

 

 

CSX

I

Low: The R61509V is selected and accessible.

IOVCC

processor

 

 

 

High: The R61509V is not selected and not accessible.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RS

I

Host

Register selection signal. (Amplitude: IOVCC-GND)

IOVCC

Low: Index register is selected.

processor

 

 

 

High: Control register is selected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write strobe signal when 80-system bus interface is selected.

 

 

 

 

 

Host

Data are written when Low level.

 

 

WRX_SCL

I

Synchronous clock signal when clock synchronous serial

IOVCC

processor

 

 

 

interface is selected.

 

 

 

 

 

 

 

 

 

 

 

 

(Amplitude: IOVCC-GND)

 

 

RDX

I

Host

Read strobe signal when 80-system bus interface is selected.

IOVCC

processor

Data are read when Low level. (Amplitude: IOVCC-GND)

 

 

 

 

 

 

 

 

Host

Serial data input pin when clock synchronous serial interface is

GND

SDI

I

selected. Data are inputted on the rising edge of SCL signal.

processor

/IOVCC

 

 

 

(Amplitude: IOVCC-GND)

 

 

 

 

 

 

 

 

 

Host

Serial data output pin when clock synchronous serial interface is

 

 

SDO

O

selected. Data are outputted on the falling edge of SCL signal.

Open

processor

 

 

 

(Amplitude: IOVCC-GND)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rev. 0.11 April 25, 2008, page 14 of 181

 

 

 

 

 

 

 

 

 

 

 

Page 13 Page 15
Page 14
Image 14
Renesas R61509V manual Pin Function, External Power Supply, Bus Interface Amplitude IOVCC~GND
Page 13 Page 15

R61509V specifications

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