Renesas R61509V manual Panel Interface Control 2 R011h

R61509V															Target Spec
	Panel Interface Control 2 (R011h)
R/W		RS	IB15	IB14	IB13	IB12	IB11	IB10	IB9	IB8	IB7	IB6	IB5	IB4	IB3	IB2	IB1	IB0
R/W		1	0	0	0	0	0	NOW	NOW	NOW	0	0	0	0	0	SDTI	SDTI	SDTI
								I[2]	I[1]	I[0]						[2]	[1]	[0]
Default			0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	1

NOWI[2:0]: Sets the non-overlap period of adjacent gate outputs. The setting is enabled when the R61509V’s display operation is synchronized with internal clock signals.

Table 24

NOWI[2:0]		Non-overlap period		NOWI[2:0]	Non-overlap period
3'h0		0 (internal clock *see note)		3'h4	4 (internal clock *see note)
3'h1		1		3'h5	5
3'h2		2		3'h6	6
3'h3		3		3'h7	7
Note:	The internal clock is the frequency		divided clock, which is set by DIVI[[1:0] bits.

SDTI[2:0]: Sets the source output delay period from the reference point. For the relationships between gate interface signals, see Liquid Crystal Panel Interface Timing.

Table 25

SDTI[2:0]	Source output delay period
3’h0	0 clocks
3’h1	1 clock
3’h2	2 clocks
3’h3	3 clocks
3’h4	4 clocks
3’h5	5 clocks
3’h6	6 clocks
3’h7	7 clocks

Notes: 1. The number of clocks in the table setting is measured from the reference point.

2.1 clock = (internal oscillation clock (OSC1) period) x (division ratio)

3.The reference point is the falling edge of gate output.

Rev. 0.11 April 25, 2008, page 55 of 181