Renesas R61509V manual SEQWI20 Source Equalize Period

R61509V Target Spec

SEQWI[2:0]: Sets source equalize period. SEQWI setting is enabled only when the R61509V executes display operation in synchronization with internal clock.

Table 27

SEQWI[2:0]	Source Equalize Period
3'h0	0 clocks
3'h1	1 clock
3'h2	2 clocks
3'h3	3 clocks
3'h4	4 clocks
3'h5	5 clocks
3'h6	6 clocks
3'h7	7 clocks

Note: The clock is the frequency divided clock, which is set by DIVI[[1:0] bits.

Rev. 0.11 April 25, 2008, page 57 of 181