Renesas R61509V manual System 9-bit Bus Interface, Bit Interface

R61509V Target Spec

80-System 9-bit Bus Interface

When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are transferred first (the LSB is not used). The RAM write data is also divided into upper and lower 9 bits, and the upper 9 bits are transferred first. The unused DB pins must be fixed at either IOVCC or IOGND level. When transferring the index register setting, make sure to write upper byte (8 bits).

			IM[2:0] = 001
	CSn		CS:
HOST	A1		RS
	HWR
			WR: R61509V
PROCESSOR
	(RDX)		(RD:)
	D15-0		DB17-9
		9	DB8-0

9

Figure 22 9-bit Interface

Instruction write
				First transfer									Second transfer
Input	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB
	17	16	15	14	13	12	11	10	9	17	16	15	14	13	12	11	10	9
Instruction	IB	IB	IB	IB	IB	IB	IB	IB		IB	IB	IB	IB	IB	IB	IB	IB
	15	14	13	12	11	10	9	8		7	6	5	4	3	2	1	0
								Instruction code
Device code read / Instruction read
Instruction	IB	IB	IB	IB	IB	IB	IB	IB		IB	IB	IB	IB	IB	IB	IB	IB
	15	14	13	12	11	10	9	8		7	6	5	4	3	2	1	0
				First transfer									Second transfer
Output	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB	DB
	17	16	15	14	13	12	11	10	9	17	16	15	14	13	12	11	10	9
									instruction code

Figure 23 9-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)

Rev. 0.11 April 25, 2008, page 104 of 181