R61509V
R61509V
112
139
Rev .11 April 25, 2008, page 5
Description
VGL
Features
Power Supply Specifications
Difference Between R61509 and R61509V
Gram
Block Diagram
Block Function
System Interface
Register Selection Clock Synchronous Serial Interface
SDO
External Display Interface RGB, Vsync interfaces
Address Counter AC
SDI
Grayscale Voltage Generating Circuit
Liquid Crystal Drive Power Supply Circuit
Internal Logic Power Supply Regulator
Graphics RAM Gram
External Power Supply
Pin Function
Bus Interface Amplitude IOVCC~GND
GND Iovcc Hsyncx
Enable
Resetx
Vsyncx
VCI1
Internal Power Supply Circuit
Protect
VDD
LCD drive
Others test, dummy pins
R61509V Pad Arrangement Rev
Type a 9381.0 251.0
Alignment marks Axis
VPP3B
DUMMYR1
DUMMYR2
AGNDDUM1
DB1
GNDDUM8
DB3
DB2
TESTO1
AGNDDUM3
AGNDDUM4
AGNDDUM5
R61509V Pad Coordinate （Unit：μm）
TESTO5
VGLDMY2
R61509V Pad Coordinate （Unit：μm）
R61509V Pad Coordinate （Unit：μm）
R61509V Pad Coordinate （Unit：μm）
TESTO9
TESTO6
TESTO7
TESTO8
R61509V Pad Coordinate （Unit：μm）
R61509V Pad Coordinate （Unit：μm）
R61509V Pad Coordinate （Unit：μm）
VGLDMY3
TESTO14
R61509V Pad Coordinate （Unit：μm）
DUMMYR4
VGLDMY4
TESTO15
DUMMYR3
Rev .11 April 25, 2008, page 36
Bump Arrangement
R61509V Wiring Example & Recommended Wiring Resistance
Gram address and display position on the panel SS = 0, BGR =
Gram Address Map
Gram address and display position on the panel SS = 1, BGR =
Instruction
Outline
Instruction Data Format
Index IR
Display control Device code read R000h
Driver Output Control R001h
LCD Drive Wave Control R002h
Entry Mode R003h
Rev .11 April 25, 2008, page 43
Automatic Address Update ORG = 0, AM, ID
Display Control 1 R007h
Display Control 2 R008h
Front and Back Porch Periods
Display Control 3 R009h
Color Control R00Bh
RAM Access Interface
External Display Interface Control 1 R00Ch
Display Interface
ENC20 Sets the RAM write cycle via RGB interface
External Display Interface Control 2 R00Fh
Panel Interface Control 1 R010h
Clocks per Line Internal Clock Operation
Division Ratio Internal Operation
Fosc
Frame Frequency Calculation
Panel Interface Control 2 R011h
Panel Interface Control 3 R012h
㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴 㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴 㪭㪚㪠㩷㫃㪼㫍㪼㫃㩷 㩷 㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋 㪞㪥㪛㩷㫃㪼㫍㪼㫃㩷
SEQWI20 Source Equalize Period
Panel Interface Control 4 R013h
Panel Interface Control 5 R014h
Division Ratio of Dotclk RGB interface operation
Panel Interface Control 6 R020h
RTNE50
Dotclkd in 1H period RGB interface operation
NOWE20 Non-overlap period
Panel Interface Control 7 R021h
Panel Interface Control 8 R022h
SEQWE20 Source Equalize Period
Mcpe 20 Vcom alternating point
Panel Interface Control 9 R023h
Frame Marker Control R090h
Constant Current in Operational Amplifiers
Power Control Power Control 1 R100h
Step-Up Factor for Step-Up Circuits
Ddvdh VCL VGH VGL
VCI1+DDVDH
Power Control 2 R101h
Step-up Frequency Step-up Circuit
Step-up clock frequency for Step-up Circuit
Line frequency
VC20 Sets VCI voltage level
DC0ｘ Value and DCDC1 Step-up Clock Signal Waveform Example
VRH30 Sets the factor to generate VREG1OUT
Power Control3 R102h
Power Control 4 R103h
Gram Address setting range
RGB
Gram Data Write R202h
Gram Read Sequence
Gram Data Read R202h
NVM Data Read / NVM Data Write R280h
Rev .11 April 25, 2008, page 79
R61509V Target Spec
Gram Address Map and Window Address Area
Control Control 1 ~ 14 R300h to R309h
R61509V Target Spec
NDL
VLE
Rev .11 April 25, 2008, page 86
Gate scan start position SCN50 SM=0 SM=1 GS=0 GS=1
Rev .11 April 25, 2008, page 88
Pin Control Test Register Software Reset R600h
’h0 Halt ’h1 Write ’h2 Setting disabled ’h3 Erase
Rev .11 April 25, 2008, page 91
R61509V Instruction List Rev 0.50 2008
RAM Data initialization
Reset Function
Initial state of instruction bits default
Initial state of input/output pins* see Note
Rev .11 April 25, 2008, page 94
OFF
Basic Mode Operation of the R61509V
Operation Modes
Interface and Data Format
RGB interface operation
Internal clock operation
Fmark interface operation
Vsync interface operation
System Interface
IM Bit Settings and System Interface
WRX R61509V
WR R61509V
R61509V
16-bit Data Transfer Synchronization
Bit Interface
System 9-bit Bus Interface
Bit Data Transfer Synchronization
System 8-bit Bus Interface
WRX R61509V
Bit Interface Data Format RAM Data Write
Rev .11 April 25, 2008, page 108
Serial Interface
Start Byte Format
Functions of RS, R/W Bits
Serial Interface Data Format
Data Transfer in Serial Interface
Vsync Interface
Vsync Interface
Example
240 ⋅ DisplayLines NL
Write/Display Operation Timing via Vsync Interface
Internal clock operation
Fmark Interface
Fmark Interface
Internal oscillation frequency fosc Hz
Main panel
FMP bit setting
One frame period
RAM physical line address
FMP Setting Example
RGB interface
RGB Interface
Polarities of VSYNCX, HSYNCX, ENABLE, and Dotclk Signals
Pcdivl
16-/18-Bit RGB Interface Timing
RGB Interface Timing
Moving Picture Display via RGB Interface
RAM access via system interface in RGB interface operation
Example of 16-Bit RGB Interface and Data Format
Bit RGB Interface
Example of 18-Bit RGB Interface and Data Format
Functions Not Available in RGB Interface operation
RGB and Internal Clock Operation Mode Switching Sequences
PTSA, Ptea
RAM Address and Display Position on the Panel
Basee VSA, VEA
Ptde Ptdp
Restrictions in Setting Display Control Instruction
Screen setting
Base image display
Display RAM Address and Panel Display Position
Full screen display no partial display
Instruction Setting Example
Partial Display
Partial only
Window Address Function
Automatic Address Update within a Window Address Area
Scan direction
Scan Mode Setting
Color Display Mode
Color Display Mode
Example of Calculation when maximum frame frequency = 60 Hz
Frame-Frequency Adjustment Function
47 Hz
Basee =
Partial Display Function
Liquid Crystal Panel Interface Timing
Rev .11 April 25, 2008, page 141
Correction Function
Correction Function
Correction Circuit
Correction Registers
Reference level adjustment registers
Reference Level Adjustment Registers and Resistors
Interpolation factor for V2 to
Interpolation Registers
Interpolation Factor for V56 to
（R2～R8/SUMR
Grayscale Voltage Calculation Formula
Frame Memory Data and the Grayscale Voltage
Power Supply Circuit Connection Example 1 VCI1 = Vciout
Power Supply Generating Circuit
R61509V
Schottky Diode
Specifications of Power-supply Circuit External Elements
Internal Logic Power Supply
Capacitor
Voltage Setting Pattern Diagram
Rev .11 April 25, 2008, page 153
Display on Sequence
Vcomh and VREG1OUT Voltage Adjustment Sequence
NVM Control
NVM Load Register Resetting Sequence
NVM Write Sequence
NVM Write Sequence
NVM Erase Sequence
NVM Erase Sequence
Power Supply on Sequence
Power Supply Setting Sequence
Power Supply OFF Sequence
Rev .11 April 25, 2008, page 161
Display ON/OFF Sequences and Refresh Sequence
Instruction Setting Sequence and Refresh Sequence
Shutdown Mode Sequences
Rev .11 April 25, 2008, page 164
Rev .11 April 25, 2008, page 165
Partial Display Setting
Color Mode Setting
Absolute Maximum Ratings
DC Characteristics
Electrical Characteristics
Rev .11 April 25, 2008, page 169
Step-up Circuit Characteristics
Internal Reference Voltage Condition
Vclv
Vcomh VREG1OUT
Power Supply Voltage Range
Output Voltage Range
VREG1O
Clock Characteristics
AC Characteristics
Pwdh
Clock Synchronous Serial Interface Timing Characteristics
RGB Interface Timing Characteristics
Pwdl
Reset Timing Characteristics （IOVCC=1.65V～3.30V）
LCD Driver Output Characteristics
Rev .11 April 25, 2008, page 175
Test Circuits
Figure a 80-system Bus Interface
Timing Characteristics System Bus Interface
Clock Synchronous Serial Interface
Figure C Reset Timing
Vsyncx
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Revision Record
