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Renesas R61509V manual Enable, Vsyncx, GND Iovcc Hsyncx, Dotclk, Fmark, IM0ID Iovcc, Resetx

Models: R61509V

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R61509V

Target Spec

18-bit parallel bi-directional data bus for 80-system interface

operation (Amplitude: IOVCC-GND).

8-bit I/F: DB17-DB10 are used.

9-bit I/F: DB17-DB9 are used.

Host

16-bit I/F: DB17-DB10 and DB8-1 are used.

GND /

DB[17:0]

I/O

18-bit I/F: DB17-DB0 are used.

processor

18-bit parallel bi-directional data bus for RGB interface operation

IOVCC

(Amplitude: IOVCC-GND).

16-bit I/F: DB17-DB13 and DB11-1 are used.

18-bit I/F: DB17-DB0 are used.

Data enable signal for RGB interface operation.

Host

Low: accessible (selected)

GND /

ENABLE

I

High: Not accessible (Not selected)

processor

IOVCC

The polarity of ENABLE signal can be inverted by setting the

EPL bit. (Amplitude: IOVCC-GND).

VSYNCX

I

Host

Frame synchronous signal. Low active. (Amplitude: IOVCC-

GND /

processor

GND).

IOVCC

HSYNCX

I

Host

Line synchronous signal, Low active. (Amplitude: IOVCC-GND)

GND /

processor

IOVCC

DOTCLK

I

Host

Dot clock signal. Data is input on the rising edge of DOTCLK.

GND /

processor

(Amplitude: IOVCC-GND)

IOVCC

FMARK

O

Host

Frame head pulse. (Amplitude: IOVCC-GND)

Open

processor

FMARK is used when writing data to the internal RAM.

Select host processor interface. (Amplitude: IOVCC-GND)

IM2

IM1

IM0

System Interface

DB pins

Colors

in use

0

0

0

80-system 18-bit

DB17-0

262,144

interface

0

0

1

80-system 9-bit

DB17-9

262,144

interface

IM2-1,

GND /

0

1

0

80-system 16-bit

DB17-10,

262,144

I

interface

8-1

(Note 1)

―

IM0_ID

IOVCC

80-system 8-bit

262,144

0

1

1

DB17-10

interface

(Note 2)

1

0

*

Clock synchronous

―

65536

(ID)

serial interface

1

1

0

Setting inhibited

―

―

1

1

1

Setting inhibited

―

―

Note 1: 65,536 colors in one-transfer operation.

Note 2: 65,536 colors in two-transfer operation.

Host

Reset pin. The R61509V is reset when RESETX is low. Make

processor

RESETX

I

sure to execute a power on reset after turning power on.

―

or external

(Amplitude: IOVCC-GND)

RC circuit

Rev. 0.11 April 25, 2008, page 15 of 181

Image 15

Renesas R61509V manual Enable, Vsyncx, GND Iovcc Hsyncx, Dotclk, Fmark, IM0ID Iovcc, Resetx

Contents

R61509V R61509V 112 139 Rev .11 April 25, 2008, page 5 Description VGL FeaturesPower Supply Specifications Difference Between R61509 and R61509V Gram Block DiagramBlock Function System InterfaceRegister Selection Clock Synchronous Serial Interface SDO External Display Interface RGB, Vsync interfacesAddress Counter AC SDIGrayscale Voltage Generating Circuit Liquid Crystal Drive Power Supply CircuitInternal Logic Power Supply Regulator Graphics RAM GramExternal Power Supply Pin FunctionBus Interface Amplitude IOVCC~GND GND Iovcc Hsyncx EnableResetx VsyncxVCI1 Internal Power Supply CircuitProtect VDDLCD drive Others test, dummy pins R61509V Pad Arrangement Rev Type a 9381.0 251.0 Alignment marks AxisVPP3B DUMMYR1DUMMYR2 AGNDDUM1DB1 GNDDUM8DB3 DB2TESTO1 AGNDDUM3AGNDDUM4 AGNDDUM5R61509V Pad Coordinate （Unit：μm） TESTO5 VGLDMY2R61509V Pad Coordinate （Unit：μm） R61509V Pad Coordinate （Unit：μm） R61509V Pad Coordinate （Unit：μm） TESTO9 TESTO6TESTO7 TESTO8R61509V Pad Coordinate （Unit：μm） R61509V Pad Coordinate （Unit：μm） R61509V Pad Coordinate （Unit：μm） VGLDMY3 TESTO14R61509V Pad Coordinate （Unit：μm） DUMMYR4 VGLDMY4TESTO15 DUMMYR3Rev .11 April 25, 2008, page 36 Bump ArrangementR61509V Wiring Example & Recommended Wiring Resistance Gram address and display position on the panel SS = 0, BGR = Gram Address MapGram address and display position on the panel SS = 1, BGR = Instruction OutlineInstruction Data Format Index IR Display control Device code read R000hDriver Output Control R001h LCD Drive Wave Control R002h Entry Mode R003hRev .11 April 25, 2008, page 43 Automatic Address Update ORG = 0, AM, ID Display Control 1 R007h Display Control 2 R008h Front and Back Porch Periods Display Control 3 R009h Color Control R00Bh RAM Access Interface External Display Interface Control 1 R00ChDisplay Interface ENC20 Sets the RAM write cycle via RGB interface External Display Interface Control 2 R00Fh Panel Interface Control 1 R010h Clocks per Line Internal Clock OperationDivision Ratio Internal Operation Fosc Frame Frequency CalculationPanel Interface Control 2 R011h Panel Interface Control 3 R012h 㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴㪭㪚㪠㩷㫃㪼㫍㪼㫃㩷㩷㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋㪞㪥㪛㩷㫃㪼㫍㪼㫃㩷SEQWI20 Source Equalize Period Panel Interface Control 4 R013h Panel Interface Control 5 R014h Division Ratio of Dotclk RGB interface operation Panel Interface Control 6 R020hRTNE50 Dotclkd in 1H period RGB interface operationNOWE20 Non-overlap period Panel Interface Control 7 R021hPanel Interface Control 8 R022h SEQWE20 Source Equalize Period Mcpe 20 Vcom alternating point Panel Interface Control 9 R023hFrame Marker Control R090h Constant Current in Operational Amplifiers Power Control Power Control 1 R100hStep-Up Factor for Step-Up Circuits Ddvdh VCL VGH VGLVCI1+DDVDH Power Control 2 R101h Step-up Frequency Step-up CircuitStep-up clock frequency for Step-up Circuit Line frequency VC20 Sets VCI voltage level DC0ｘ Value and DCDC1 Step-up Clock Signal Waveform Example VRH30 Sets the factor to generate VREG1OUT Power Control3 R102hPower Control 4 R103h Gram Address setting range RGB Gram Data Write R202hGram Read Sequence Gram Data Read R202hNVM Data Read / NVM Data Write R280h Rev .11 April 25, 2008, page 79 R61509V Target Spec Gram Address Map and Window Address Area Control Control 1 ~ 14 R300h to R309h R61509V Target Spec NDL VLE Rev .11 April 25, 2008, page 86 Gate scan start position SCN50 SM=0 SM=1 GS=0 GS=1 Rev .11 April 25, 2008, page 88 Pin Control Test Register Software Reset R600h ’h0 Halt ’h1 Write ’h2 Setting disabled ’h3 Erase Rev .11 April 25, 2008, page 91 R61509V Instruction List Rev 0.50 2008 RAM Data initialization Reset FunctionInitial state of instruction bits default Initial state of input/output pins* see NoteRev .11 April 25, 2008, page 94 OFF Basic Mode Operation of the R61509VOperation Modes Interface and Data FormatRGB interface operation Internal clock operationFmark interface operation Vsync interface operationSystem Interface IM Bit Settings and System InterfaceWRX R61509V WR R61509V R61509V 16-bit Data Transfer Synchronization Bit Interface System 9-bit Bus InterfaceBit Data Transfer Synchronization System 8-bit Bus Interface WRX R61509VBit Interface Data Format RAM Data Write Rev .11 April 25, 2008, page 108 Serial Interface Start Byte FormatFunctions of RS, R/W Bits Serial Interface Data Format Data Transfer in Serial Interface Vsync Interface Vsync InterfaceExample 240 ⋅ DisplayLines NLWrite/Display Operation Timing via Vsync Interface Internal clock operation Fmark Interface Fmark InterfaceInternal oscillation frequency fosc Hz Main panel FMP bit settingOne frame period RAM physical line address FMP Setting ExampleRGB interface RGB InterfacePolarities of VSYNCX, HSYNCX, ENABLE, and Dotclk Signals Pcdivl 16-/18-Bit RGB Interface Timing RGB Interface TimingMoving Picture Display via RGB Interface RAM access via system interface in RGB interface operationExample of 16-Bit RGB Interface and Data Format Bit RGB InterfaceExample of 18-Bit RGB Interface and Data Format Functions Not Available in RGB Interface operation RGB and Internal Clock Operation Mode Switching SequencesPTSA, Ptea RAM Address and Display Position on the PanelBasee VSA, VEA Ptde PtdpRestrictions in Setting Display Control Instruction Screen settingBase image display Display RAM Address and Panel Display Position Full screen display no partial display Instruction Setting ExamplePartial Display Partial onlyWindow Address Function Automatic Address Update within a Window Address AreaScan direction Scan Mode SettingColor Display Mode Color Display ModeExample of Calculation when maximum frame frequency = 60 Hz Frame-Frequency Adjustment Function47 Hz Basee = Partial Display FunctionLiquid Crystal Panel Interface Timing Rev .11 April 25, 2008, page 141 Correction Function Correction FunctionCorrection Circuit Correction Registers Reference level adjustment registersReference Level Adjustment Registers and Resistors Interpolation factor for V2 to Interpolation RegistersInterpolation Factor for V56 to （R2～R8/SUMR Grayscale Voltage Calculation FormulaFrame Memory Data and the Grayscale Voltage Power Supply Circuit Connection Example 1 VCI1 = Vciout Power Supply Generating CircuitR61509V Schottky Diode Specifications of Power-supply Circuit External ElementsInternal Logic Power Supply CapacitorVoltage Setting Pattern Diagram Rev .11 April 25, 2008, page 153 Display on Sequence Vcomh and VREG1OUT Voltage Adjustment SequenceNVM Control NVM Load Register Resetting Sequence NVM Write Sequence NVM Write SequenceNVM Erase Sequence NVM Erase SequencePower Supply on Sequence Power Supply Setting SequencePower Supply OFF Sequence Rev .11 April 25, 2008, page 161 Display ON/OFF Sequences and Refresh Sequence Instruction Setting Sequence and Refresh SequenceShutdown Mode Sequences Rev .11 April 25, 2008, page 164 Rev .11 April 25, 2008, page 165 Partial Display Setting Color Mode SettingAbsolute Maximum Ratings DC Characteristics Electrical CharacteristicsRev .11 April 25, 2008, page 169 Step-up Circuit Characteristics Internal Reference Voltage ConditionVclv Vcomh VREG1OUT Power Supply Voltage RangeOutput Voltage Range VREG1OClock Characteristics AC CharacteristicsPwdh Clock Synchronous Serial Interface Timing CharacteristicsRGB Interface Timing Characteristics PwdlReset Timing Characteristics （IOVCC=1.65V～3.30V） LCD Driver Output CharacteristicsRev .11 April 25, 2008, page 175 Test Circuits Figure a 80-system Bus Interface Timing Characteristics System Bus InterfaceClock Synchronous Serial Interface Figure C Reset TimingVsyncx Renesas Sales Offices Revision Record