R61509V | Target Spec |
Serial Interface
The serial interface is selected by setting the IM2/1 pins to the IOVCC/GND levels, respectively. The data is transferred via chip select line (CS), serial transfer clock line (SCL), serial data input line (SDI), and serial data output line (SDO). In serial interface operation, the IM0_ID pin functions as the ID pin, and the
The R61509V recognizes the start of data transfer on the falling edge of CSX input and starts transferring the start byte. It recognizes the end of data transfer on the rising edge of CSX input. The R61509V is selected when the
When writing data to the GRAM via serial interface, the data is written to the GRAM after it is transferred in two bytes. The R61509V writes data to the GRAM in units of 18 bits by adding the same bits as the MSBs to the LSB of R and B dot data.
After receiving the start byte, the R61509V starts transferring or receiving data in units of bytes. The R61509V transfers data from the MSB. The R61509V’s instruction consists of 16 bits and it is executed inside the R61509V after it is transferred in two bytes (16 bits:
When reading data from the GRAM, valid data is not transferred to the data bus until first five bytes of data are read from the GRAM following the start byte. The R61509V sends valid data to the data bus when it reads the sixth and subsequent byte data.
Table 58 Start Byte Format
| Transferred Bits | S | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
Start byte format | Transfer start | Device ID code |
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| RS | R/W | |||
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| 0 | 1 | 1 | 1 | 0 | ID | ||
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Note: | The ID bit is determined by setting the IM0_ID pin. |
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Table 59 Functions of RS, R/W Bits
RS | R/W | Function |
0 | 0 | Set index register |
0 | 1 | Setting inhibited |
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1 | 0 | Write instruction or RAM data |
1 | 1 | Read instruction or RAM data |
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Rev. 0.11 April 25, 2008, page 109 of 181