■DC0x Value and DCDC1 Step-up Clock Signal Waveform Example

DCDC1 performs charge operation and boost operation with the step-up clock generated from the timing generator.

The DCDC1 step-up clock frequency is adjusted by setting the division ratio of the reference clock frequency with DC0x register. (To prevent flickering, the DCDC1 step-up clock signal is synchronized with the reference point of display operation in unit of lines.) Note: Set DC0x and RTNx so that (DCDC1 step-up clock frequency) ≧ (line clock frequency)

If the above restriction is not followed, the duty cycle during the boost period is less than 50%. As a result, the step-up circuit may not operate normally.

Example) DIVn=2'h0, RTN=5'h19 (reference clock period = 1/1 of internal operation clock, 1H period = 25 clocks)

Reference clock

Reference clock counter

a) DC0x=3'h4

(1/8 of reference clock frequency)

DCDC1 step-up clock

b) DC0x=3'h5

(1/16 of reference clock frequency)

DCDC1 step-up clock

c) DC0x=3'h6

(1/32 of reference clock frequency)

DCDC1 step-up clock

Reference point

 

1H period

 

 

 

 

 

 

 

 

 

 

Reference point

 

 

 

 

 

 

 

 

 

 

 

 

 

5'h10 5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08 5'h09

5'h0A

5'h0B 5'h0C 5'h0D

5'h0E

5'h0F

5'h10

5'h11

5'h12

5'h13

5'h14

5'h15

5'h16

5'h17

5'h18 5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08

Synchronized with the reference point in unit of lines

 

 

 

 

 

 

 

 

 

 

 

 

Synchronized with the reference point in unit of lines

8 clock cycles

 

8 clock cycles

 

 

 

 

 

8 clock cycles

 

 

 

 

16 clock cycles

 

 

 

 

 

 

 

 

 

 

 

 

 

32 clock cycles (As the number of clocks per 1H period is less than 32, the duty cycle of the step-up clock is not 50%.

 

 

 

 

 

 

Note: The duty cycle of the step-up clock should be close to 50%.

■DC1x Value and DCDC2 Step-up Clock Signal Waveform Example

DCDC2 performs charge operation and boost operation with the step-up clock generated from the timing generator.

The DCDC2 step-up clock frequency is adjusted by setting the division ratio of the reference clock frequency with DC1x register. (To prevent flicker, the DCDC2 step-up clock signal is synchronized with the head of BP period in unit of lines.)

Example) BP=FP=8'h08, NL=7'h6B (front porch = back porch 8 lines, the number of lines to drive the LCD = 432 lines)

Reference

Reference

Reference

Reference

Reference

Reference

Reference

Reference Reference Reference Reference Reference Reference Reference

Reference

Reference

Reference

Reference Reference Reference Reference Reference Reference Reference Reference Reference

Reference

Reference

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

point

1H period 1H period 1H period

Reference clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Line clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Counter for the number of lines

'h1BE 'h1BF

'h000 'h001 'h002 'h003 'h004

'h005 'h006 'h007 'h008

'h009 'h00A

'h00B 'h00C

'h00D 'h00E

'h00F

'h010

'h011

'h012

'h013

'h014

'h015

'h016

'h017

'h018

'h019

 

Front Porch

Back Porch

 

Display Area

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronized with the head of BP period

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

a) DC1x=3'h2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1/4 of line clock frequency)

 

4H cycles

4H cycles

 

4H cycles

 

4H cycles

 

 

 

 

 

 

 

 

 

 

 

DCDC2 step-up clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

b) DC1x=3'h3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1/8 of line clock frequency)

 

8H cycles

 

 

 

8H cycles

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DCDC2 step-up clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

c) DC0x=3'h4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1/16 of line clock frequency)

 

 

16H cycles

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DCDC2 step-up clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Page 72
Image 72
Renesas R61509V manual DC0x Value and DCDC1 Step-up Clock Signal Waveform Example

R61509V specifications

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