Renesas R61509V manual Panel Interface Control 7 R021h, NOWE20 Non-overlap period

R61509V Target Spec

Panel Interface Control 7 (R021h)

R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0

R/W 1

Default

0	0	0	0	0	NOW	NOW	NOW	0	0	0	0	0	SDTE	SDTE	SDTE
					E[2]	E[1]	E[0]						[2]	[1]	[0]
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	1

NOWE[2:0]: Sets the non-overlap period of adjacent gate outputs. NOWE is enabled when RGB interface is selected.

Table 33

NOWE[2:0] Non-overlap period

3’h0	0 clocks
3’h1	1 clock
3’h2	2 clocks
3’h3	3 clocks
3’h4	4 clocks
3’h5	5 clocks
3’h6	6 clocks
3’h7	7 clocks
Note:	1 clock = (number of data transfer/pixel) x DIVE (division ratio) x (PCDIVL + PCDIVH) [DOTCLK]

SDTE[2:0]: Sets the source output delay period from the reference point when the R61509V’s display operation is synchronized with DOTCLK (DM = 2’h1). For the relationships between signals, see Liquid Crystal Panel Interface Timing.

Table 34

SDTE[2:0]	Source output delay period
3’h0	0 clocks
3’h1	1 clock
3’h2	2 clocks
3’h3	3 clocks
3’h4	4 clocks
3’h5	5 clocks
3’h6	6 clocks
3’h7	7 clocks

Notes: 1. The number of clocks in the table setting is measured from the reference point.

2.1 clock = DOTCLKD (when pixel data is transferred in one- transfer)

3.The reference point is falling edge of gate control signals.

Rev. 0.11 April 25, 2008, page 62 of 181