4.5.3 Active to Precharge Delay
The default setting for the Active to Precharge Delay is 7.
4.5.4 DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address Strobe) and CAS (Column Address Strobe) signals. This delay occurs when the SDRAM is written to, read from or refreshed. Reducing the delay improves the performance of the SDRAM.
4.5.5 DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to accumulate its charge before the SDRAM refreshes. The default setting for the Active to Precharge Delay is 3.
4.5.6 DRAM Data Integrity Mode
Select ECC if your memory module supports it. The memory controller will detect and correct
4.5.7 MGM Core Frequency
This field sets the frequency of the DRAM memory installed. The default setting is Auto Max 266MHz.
4.5.8 System BIOS Cacheable
The setting of Enabled allows caching of the system BIOS ROM at
4.5.9 Video BIOS Cacheable
The Setting Enabled allows caching of the video BIOS ROM at C0000h- F7FFFh, resulting in better video performance. However, if any program writes to this memory area, a system error may result.
4.5.10 Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be reserved for ISA cards. This memory must be mapped into the memory space below 16 MB. The choices are Enabled and Disabled.
4.5.11 Delayed Transaction
The chipset has an embedded
4.5.12 Delay Prior to Thermal
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