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User’s Manual for Advantech SOM-A2552 series module V1.00
27
B19
BUF_DQM0 O
SDRAM DQM for data byte 0.
Connect to the data output mask
enables (DQM) for SDRAM. No pulling
A19
BUF_DQM2 O
SDRAM DQM for data byte 2.
Connect to the data output mask
enables (DQM) for SDRAM. No pulling
B20
BUF_DQM3 O
SDRAM DQM for data byte 3.
Connect to the data output mask
enables (DQM) for SDRAM. No pulling
A20
nBUF_PWAIT
I
PCMCIA wait. (input)
Driven low by
the PCMCIA card to extend the
length of the transfers to/from the
PXA255 processor.
Pull high
with
100Kohm
B21
BUF_SDCLK
1 O
SDRAM Clock 1.
Connect SDCLK
[1] to the clock pins of SDRAM in
bank pairs 0/1. They are driven by
either the interna
l memory controller
clock, or the internal memory
controller clock divided by 2. At
reset, all clock pins are free running
at the divide by 2 clock speed and
may be turned off via free running
control register bits in the memory
controller. The memory cont
roller
also provides control register bits for
clock division and deassertion of
each SDCLK pin. SDCLK[2:1]
control register assertion bits are
always deasserted upon reset.
No pulling
A21
BUF_SDCKE
1 O
SDRAM and/or Synchronous Static
Memory clock enable.
Connect to
the clock enable pins of SDRAM. It is
deasserted during sleep.
BUF_SDCKE1 is always deasserted
upon reset. The memory controller
provides control register bits for
deassertion.
No pulling
(For
SOM-
255F
is
BUF_SDC
KE1)
B22
GND P Ground -
A22
ADDR0 O SoC PXA255 system address 0 No pulling
B23
ADDR1 O SoC PXA255 system address 1 No pulling
A23
ADDR2 O SoC PXA255 system address 2 No pulling
B24
ADDR3 O SoC PXA255 system address 3 No pulling
A24
ADDR4 O SoC PXA255 system address 4 No pulling
B25
ADDR5 O SoC PXA255 system address 5 No pulling
A25
ADDR6 O SoC PXA255 system address 6 No pulling
B26
ADDR7 O SoC PXA255 system address 7 No pulling
A26
ADDR16 O SoC PXA255 system address 16 No pulling
B27
ADDR17 O SoC PXA255 system address 17 No pulling
A27
ADDR18 O SoC PXA255 system address 18 No pulling