Your ePlatform Partner
User’s Manual for Advantech
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| Sync input of the LCD panel. For |
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| STN displays, this output connects |
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| to the Frame Clock input of the |
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| LCD panel. |
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| This output indicates the start of a |
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| new frame of pixels. The panel |
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| needs to reset its line pointers to |
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| the top of the screen. |
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197 | LP_HSYNC | O | Flat Panel TFT Vertical Sync/STN | No pulling |
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| Frame Pulse. For TFT displays, |
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| this output connects to the Vertical |
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| Sync input of the LCD panel. For |
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| STN displays, this output connects |
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| to the Frame Clock input of the |
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| LCD panel. |
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|
| This output indicates the start of a |
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| new frame of pixels. The panel |
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|
| needs to reset its line pointers to |
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| the top of the screen. |
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198 | GND | P | Ground | - |
199 | M_DE | O | Flat Panel Display Enable. This | No pulling |
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| signal is used as a data enable |
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| when the pixel clock needs to latch |
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| pixel data. |
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200 | SHCLK | O | Flat Panel Pixel Clock. The active | No pulling |
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| edge of FPCLK is programmable. |
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| The LCD panel uses this clock |
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| when loading pixel data into its |
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| Line Shift register. This signal |
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| connects to the TXCLK input of the |
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| LVDS transmitter. |
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Pin | Signals | Type |
| Description |
| Default |
No. |
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| state | |||
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| Static chip selects. Chip selects to |
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| static memory devices such as ROM |
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| and | Flash. | Individually |
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| programmable in the | memory |
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| configuration registers. This pin can | |||
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| be used | with variable latency I/O | ||
B1 | nBUF_CS2 | O | with 100K | |||
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| devices. nBUF_CS2 directly connect | ohm | ||
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| to SoC PXA255 nCS2. User could | |||
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| use this pin as chip select pin to |
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| control the solution IC on carrier |
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| board. This pin is reserved for user |
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| to use. |
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