Patch 86241-06 For Rapier Switches

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into 8 blocks of 85 bits with 84 bits available for payload, and one bit for framing overhead. The frame structure is shown in Figure 1 on page 23.

Figure 1: DS3 Framing Structure.

M-Frame 4760 bits

X1 679 X2

Bits

679

P1

679

P2

679

M1

679

M2

679

M3

679

Bits

 

Bits

 

Bits

 

Bits

 

Bits

 

Bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

First M-Subframe 680 bits

X1 84 INFO

F1 84 INFO

C1 84 INFO

F2 84 INFO

C2 84 INFO

F3 84 INFO

C3 84 INFO

F4 84 INFO

DS31

The switch with the DS3 interface is called the near end. The entity the switch connects to is called the far end. X1 and X2 are set to 1 if the near end is receiving an Alarm Indication Signal (AIS), a Loss Of Frame (LOF), or a Loss Of Signal (LOS). This allows the near end to indicate to the far end that it is experiencing a problem and is known as Far End Receive Failure (FERF).

P1 and P2 form the P-bit channel. They provide parity information for the preceding M-frame.

M1, M2, and M3 form a frame alignment channel used by the hardware to locate all seven M-subframes.

F1, F2, F3, and F4 form an M-subframe alignment channel which is used by the hardware to identify all frame overhead bit positions.

C1, C2, and C3 form the C-bit channel.

C-bit Parity Mode

In C-bit parity mode the C-bits are described as follows:

The first C-bit in M-subframe 1 is set to 1 to identify the format as C-bit parity. If this is zero the format is assumed to be M23.

The second C-bit in M-subframe 1 is designated Nr and is set to 1.

The third C-bit in M-subframe 1 provides the Far End Alarm and Control signal (FEAC) which is used to:

Send alarm or status information from the far end back to the near end.

Initiate DS3 loopbacks.

The three C-bits in M-subframe 3 are designated as CP-bits and are used to implement CP-bit parity. At the near end the CP-bits are set to the same value as the P-bits. The parity of the CP-bits of frame N are compared with the parity of the CP-bits of frame N+1. A difference in parity between N and N+1 is deemed a CP-bit parity error.

Patch 86241-05 for Software Release 2.4.1 C613-10340-00 REV E

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Allied Telesis 86241-06 manual Bit Parity Mode