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AMX 68000 Target Guide
1.5 Launch Requirements
The M68000 must be properly configured for use before AMX is launched. The manner
in which this is accomplished will depend on your target hardware implementation and
on the startup code provided with your C compiler.
AMX does not include bootstrap code to initialize the M68000 processor. It is assumed
that you will have a boot ROM present which configures the M68000 for your specific
hardware configuration and begins program execution at the entry to your C startup code.
During development, you may be using a ROM monitor provided by the processor
vendor or by the toolset supplier. The ROM monitor automatically initializes the
processor at power on. The monitor is then used to download your AMX application and
start execution at the entry point to the C startup code. Eventually your main C program
is called and AMX can be launched by your call to cjkslaunch.
Once your application has been tested, you may choose to replace the ROM monitor and
the C startup code with your own initialization code. The manner in which you do this is
outside the scope of this manual.
Operating Mode
AMX requires that the processor be set to supervisor mode. The processor is in
supervisor mode when the supervisor/user state bit S is 1 in the status register (SR). This
is the default state when the processor is reset.
Interrupt State
Interrupts can be enabled or disabled on entry to AMX. Set the interrupt priority mask in
the status register to disable (0x0600) or enable (0x0000) external interrupts. AMX will
disable interrupts during its startup initialization. AMX will enable interrupts prior to
calling your application Restart Procedures.
If you launch AMX with interrupts enabled, be sure that all interrupt sources are either
disabled or externally masked off. You must not enable or unmask any interrupt source
until you have installed an AMX Interrupt Service Procedure to properly service the
device. This subject is described in more detail in Chapters 3 and 4.
For the MC68020, MC68030, MC68040, MC68060 and architecturally similar
processors, AMX requires that the processor be set to interrupt mode. The processor is
in interrupt mode when the master/interrupt state bit M is 0 in the status register (SR). This
is the default state when the processor is reset.
Some M68000 processors include a Vector Base Register (VBR) which must be
initialized with the address of the Exception Vector Table. AMX can be configured to do
this initialization at launch time. Alternatively you can initialize the VBR prior to
launching AMX and allow AMX to read the VBR without modifying it.