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AMX 68000 Target Guide
3.5 Nonconforming ISPsThe M68000 family of processors provides an interrupt priority ordering mechanism
which permits the use of nonconforming ISPs within an AMX system. Since
nonconforming ISPs bypass the AMX Interrupt Supervisor, they cannot make use of any
AMX services.
Nonconforming ISPs run at the interrupt priority level dictated by the interrupt source. A
nonconforming ISP must NOT set the interrupt priority level to any level numerically
lower than the level of the interrupt which it is servicing. Higher priority interrupts are
only allowed if the corresponding ISPs are also nonconforming ISPs.
A nonconforming ISP must NOT allow an interrupt from ANY higher priority
conforming ISP. Remember that, in this context, the ISP for the device which generates
the AMX clock interrupt is considered to be a conforming ISP.
Upon entry to a nonconforming ISP the processor state matches its state at the time of the
interrupt. The processor is in supervisor mode with interrupts disabled at priority level n
(0 to 6) in the status register. No registers are free for use. All registers must be
preserved.
The nonconforming ISP executes on the stack in effect at the time of the interrupt.
Hence, the nonconforming ISP may execute on any task stack including the AMX Kernel
Task's stack. A nonconforming ISP will execute on the AMX Interrupt Stack if the
nonconforming ISP interrupts a conforming ISP.
The nonconforming ISP must service the device to remove the interrupt request and
dismiss the interrupt with an RTE instruction.