AMX 68000, Target Guide - page 13

AMX 68000 Target Guide
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Trace Controls
AMX alters the state of the status register (SR) whenever it enables or disables interrupts.
When AMX disables interrupts, it also clears the trace control bits (T or T0 and T1) to 0.
When AMX enables interrupts, the trace control bits remain unaltered. Consequently,
you may not be able to use your debugger to single step trace through private AMX code
sequences.
M68000 Stack Use
The M68000 begins execution in supervisor mode (and interrupt mode for the MC68020,
MC68030, MC68040, MC68060, et al) using the initial interrupt stack specified by
vector number 0 in the Exception Vector Table. Your bootstrap code or C startup code
may switch to an alternate stack. Once AMX is launched, it abandons the startup stack.
AMX only uses the stacks allocated by you in your AMX System Configuration Module.
To accomplish this feat on processors which support multiple stacks, AMX always
executes in the interrupt mode (M = 0 in SR).
Instruction and Data Caching
The MC68020 includes a 256-byte instruction cache but no data cache.
The MC68030 includes a 256-byte instruction cache and a 256-byte data cache.
The MC68040 includes a 4096-byte instruction cache and a 4096-byte data cache.
The MC68060 includes an 8192-byte instruction cache and an 8192-byte data cache.
If your AMX Target Parameter File (see Chapter 4) targets one of these processors, AMX
will automatically flush and enable both caches when AMX is launched. Alternatively,
you can configure AMX to ignore the caches during the launch. AMX provides
procedures which you can use to enable or disable the caches.
For example, if you disable both caches in your main program and configure AMX to
ignore the cache, you can simplify the initial testing of your application or overcome
caching problems which may be encountered if your debugger cannot properly handle
cached operation.
You must be aware that, on processors which utilize an M68000 Memory Management
Unit (MMU), successful cache operation will depend on proper setup of the MMU. For
example, if the MMU does not properly control cached access to memory and devices,
you may find that device I/O reads and writes end up being cached, resulting in failure of
the device to operate as expected.
AMX does not manipulate the MMU. If you configure AMX to enable caching during
the launch, then you must ensure that the MMU is properly initialized to meet your
hardware memory addressing specifications prior to launching AMX. The AMX Sample
Program purposely leaves the caches unaltered to avoid possible cache related problems
during your initial use of AMX in your hardware environment.