Functional Description
ARM DDI 0397G Copyright ©2006-2010 ARM. All rights reserved. 2-7
ID031010 Non-Confidential
Note
When communicating with transfer-sensitive slave devices such as FIFOs, the master might not
be aware of how many read data beats have been read.
Lock transactions
The only supported lock transactions are SWP-like locks. That is, a single locking read followed
by a single unlocking write, with an undefined number of IDLE transactions in between.
Note
If the network receives a non-SWP-like lock sequence, it is possible for a network path to be
stalled, particularly if an odd number of lock transactions is issued. The stall is cancelled on the
next transaction received that unlocks the stalled path.
If you configure lock support and a GPV, then a lock override function is also configured. You
can program this option, named
lock_override
, to force no AXI lock transactions to be created.
See Chapter3 Programmers Model.
Configuration options
You can configure the following AHB options:
• AHB slave or master mirror interface types.
• Address width of 32-64 bits.
• Data width of 32. 64, 128, or 256 bits.
• Data width upsize function that Upsizing data width function on page 2-12 describes.
• Data width downsize function that Downsizing data width function on page 2-14
describes.
• Frequency domain crossing of the following types:
—ASYNC
—SYNC 1:1
—SYNC 1:n
—SYNC n:1
—SYNC n:m.
• Security of the following types:
Secure All transactions originating from this slave interface are flagged as secure
transactions and can access both secure and non-secure components.
Non-secure
All transactions originating from this slave interface are flagged as non-secure
transactions and cannot access secure components.
•
INCR promotion and Early Write Response
.
• Permit broken bursts using the
allow broken bursts
parameter.
• Support for the full AHB-Lite protocol with only SWAP-like locks.
Note
You can reduce the gate count and increase the performance if the attached master does
not create any AHB lock transactions.