ARM NIC-301 Table3-3 shows the registers that exist for each AMIB.

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Table3-3 shows the registers that exist for each AMIB.
0x044 -- - - Reserved.
0x100 -- - - Reserved.
0x104 -- - - Reserved.
0x108 RW 2 0 fn_mod_iss Issuing functionality modification register.
Issuing override, sets block issuing capability to one transaction and
you can configure the bits as follows:
0 Read issuing,
read_iss_override .
1 Write issuing,
write_iss_override .
0x10C -- - - Reserved
0x110 -- - - Reserved
a. The reset value is initialized to the tidemark value that you set in the configuration GUI in AMBA Designer (ADR-301).
Table3-2 Registers for each IB (continued)
Address
offset Type Wi dth Reset value Name Description
Table3-3 Registers for each AMIB
Address
offset Type Wi dth Reset value Name Description
0x000 ---- Reserved.
0x004 ---- Reserved.
0x008 RW 2 0 fn_mod_bm_iss Bus matrix issuing functionality modification register. This register is
only present if the block is connected directly to a switch.
This register sets the issuing capability of the preceding switch arbitration
scheme to 1. You can configure the register bits as follows:
0 Read issuing,
read_iss_override .
1 Write issuing,
write_iss_override .
0x00C ---- Reserved.
0x020 RW 3 4 Sync_mode This register is only available if you have a FIFO for all channels. You can
configure the register bits to create different clock domain boundaries as
follows:
0 sync 1:1.
1 sync n:1.
2 sync 1:n.
3 sync m:n.
4 async.
5 reserved.
6 reserved.
7 reserved.
0x024 RW 1 0 fn_mod2 Bypass merge. This register is only present if upsizing or downsizing. See
Upsizing data width function on page2-12 and Downsizing data width
function on page2-14.
0x028 ---- Reserved.