Glossary
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Advanced Peripheral Bus (APB)
A simpler bus protocol than AXI and AHB. It is designed for use with ancillary or
general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports.
Connection to the main system bus is through a system-to-peripheral bus bridge that helps to
reduce system power consumption.
AHB See Advanced High-performance Bus.
AHB-Lite A subset of the full AMBA AHB protocol specification. It provides all of the basic functions
required by the majority of AMBA AHB slave and master designs, particularly when used with
a multi-layer AMBA interconnect. In most cases, the extra facilities provided by a full AMBA
AHB interface are implemented more efficiently by using an AMBA AXI protocol interface.
Aligned A data item stored at an address that is divisible by the number of bytes that defines the data size
is said to be aligned. Aligned words and halfwords have addresses that are divisible by four and
two respectively. The terms word-aligned and halfword-aligned therefore stipulate addresses
that are divisible by four and two respectively.
AMBA See Advanced Microcontroller Bus Architecture.
APB See Advanced Peripheral Bus.
AXI See Advanced eXtensible Interface.
AXI channel order and interfaces
The block diagram shows:
• the order in which AXI channel signals are described
• the MI and SI conventions for AXI components.
AXI terminology The following AXI terms are general. They apply to both masters and slaves:
Active read transaction
A transaction for which the read address has transferred, but the last read data has
not yet transferred.
Active transfer
A transfer for which the xVALID handshake has asserted, but for which
xREADY has not yet asserted.
Note
The letter x in the signal name denotes an AXI channel as follows:
AW Write address channel.
W Write data channel.
B Write response channel.
AR Read address channel.
R Read data channel.
AXI
interconnect
Write address channel (AW)
Write data channel (W)
Write response channel (B)
Read address channel (AR)
Read data channel (R)
Write address channel (AW)
Write data channel (W)
Write response channel (B)
Read address channel (AR)
Read data channel (R)
AXI slave
interface
AXI master
interface
AXI
master
AXI
slave
AXI master
interface
AXI slave
interface