POST | Function | Phase | Component | |
Code | ||||
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0x12 | TIS wait command ready failed (prepare to send) | DXE | TCG | |
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0x12 | TIS abort 'send 'command due to timeout | DXE | TCG | |
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0x12 | TIS abort 'sendAndGo 'command due to timeout | DXE | TCG | |
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0x04 | TIS wait bit set failed before send last byte | DXE | TCG | |
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0x12 | TIS abort command due to timeout before send last byte | DXE | TCG | |
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0x04 | TIS wait bit clear failed when sending last byte | DXE | TCG | |
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0x22 | TCG Physical Presence execution | DXE | TCG | |
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0xB1 | TCG DXE common pass through | DXE | TCG | |
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0xE3 | First Legacy BIOS Task table for legacy reset | LBT | Core | |
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0x20 | Verify that DRAM refresh is operating by polling the refresh bit | LBT | Core | |
| in PORTB. |
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0xDA | Dummy PCIE Init entry, now handled by driver | LBT | Core | |
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0x29 | PMM (POST Memory Manager) init | LBT | Core | |
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0xE5 | WHEA init | LBT | Core | |
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0x33 | PDM (Post Dispatcher Manager) init | LBT | Core | |
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0x01 | IPMI init | LBT | Core | |
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0xD8 | ASF Init | LBT | Core | |
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0x09 | Set | LBT | Core | |
| this bit is not cleared by postClearBootFlagJ(AEh), the |
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| TrustedCore on next boot determines that the current |
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| configuration caused POST to fail and uses default values for |
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| configuration. |
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0x2B | Enhanced CMOS init | LBT | Core | |
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0xE0 | EFI Variable Init | LBT | Core | |
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0xC1 | PEM (Post Error Manager) init | LBT | Core | |
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0x3B | Debug Service Init (ROM Polit) | LBT | Core | |
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0xDC | POST Update Error | LBT | Core | |
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0x3A | Autosize external cache and program cache size for enabling | LBT | Core | |
| later in POST. |
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0x0B | Enable CPU cache. Set bits in cmos related to cache. | LBT | Core | |
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0x0F | Enable the local bus IDE as primary or secondary depending | LBT | Core | |
| on other drives detected. |
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0x10 | Initialize Power Management. | LBT | Core | |
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0x14 | Verify that the 8742 keyboard controller is responding. Send a | LBT | Core | |
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| the switch inputs from the 8742 and write the keyboard |
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| controller command byte. |
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0x1A | Initialize DMA command register with these settings: | LBT | Core |
1.Memory to memory disabled
2.Channel 0 hold address disabled
3.Controller enabled
4.Normal timing
5.Fixed priority
6.Late write selection
7.DREQ sense active
8.DACK sense active low. Initialize
Chapter 4 | 141 |
